📄 cpu_test_bench.v
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assign W_op_andi = W_iw_op[5 : 0] == 12;
assign W_op_ldw = W_iw_op[5 : 0] == 23;
assign W_op_stb = W_iw_op[5 : 0] == 5;
assign W_op_cmpgei = W_iw_op[5 : 0] == 8;
assign W_op_opx = W_iw_op[5 : 0] == 58;
assign W_op_rsv41 = W_iw_op[5 : 0] == 41;
assign W_op_rsv25 = W_iw_op[5 : 0] == 25;
assign W_op_rsv09 = W_iw_op[5 : 0] == 9;
assign W_op_ldhuio = W_iw_op[5 : 0] == 43;
assign W_op_rsv42 = W_iw_op[5 : 0] == 42;
assign W_op_rsv26 = W_iw_op[5 : 0] == 26;
assign W_op_andhi = W_iw_op[5 : 0] == 44;
assign W_op_rsv61 = W_iw_op[5 : 0] == 61;
assign W_op_rsv29 = W_iw_op[5 : 0] == 29;
assign W_op_sth = W_iw_op[5 : 0] == 13;
assign W_op_rsv62 = W_iw_op[5 : 0] == 62;
assign W_op_rsv63 = W_iw_op[5 : 0] == 63;
assign W_op_flushd = W_iw_op[5 : 0] == 59;
assign W_op_ldhio = W_iw_op[5 : 0] == 47;
assign W_op_rsv49 = W_iw_op[5 : 0] == 49;
assign W_op_orhi = W_iw_op[5 : 0] == 52;
assign W_op_flushda = W_iw_op[5 : 0] == 27;
assign W_op_call = W_iw_op[5 : 0] == 0;
assign W_op_cmpeqi = W_iw_op[5 : 0] == 32;
assign W_op_ldwio = W_iw_op[5 : 0] == 55;
assign W_op_custom = W_iw_op[5 : 0] == 50;
assign W_op_stw = W_iw_op[5 : 0] == 21;
assign W_op_ldbu = W_iw_op[5 : 0] == 3;
assign W_op_stbio = W_iw_op[5 : 0] == 37;
assign W_op_rsv10 = W_iw_op[5 : 0] == 10;
assign W_op_cmpgeui = W_iw_op[5 : 0] == 40;
assign W_op_xori = W_iw_op[5 : 0] == 28;
assign W_op_rsv31 = W_iw_op[5 : 0] == 31;
assign W_op_addi = W_iw_op[5 : 0] == 4;
assign W_op_ldhu = W_iw_op[5 : 0] == 11;
assign W_op_rsv33 = W_iw_op[5 : 0] == 33;
assign W_op_rsv17 = W_iw_op[5 : 0] == 17;
assign W_op_rsv34 = W_iw_op[5 : 0] == 34;
assign W_op_bne = W_iw_op[5 : 0] == 30;
assign W_op_rsv18 = W_iw_op[5 : 0] == 18;
assign W_op_rsv19 = W_iw_op[5 : 0] == 19;
assign W_op_xorhi = W_iw_op[5 : 0] == 60;
assign W_op_rsv56 = W_iw_op[5 : 0] == 56;
assign W_op_bltu = W_iw_op[5 : 0] == 54;
assign W_op_rsv57 = W_iw_op[5 : 0] == 57;
assign W_op_ldbuio = W_iw_op[5 : 0] == 35;
assign W_op_ldb = W_iw_op[5 : 0] == 7;
assign W_op_sthio = W_iw_op[5 : 0] == 45;
assign W_op_initd = W_iw_op[5 : 0] == 51;
assign W_op_blt = W_iw_op[5 : 0] == 22;
assign W_op_cmplti = W_iw_op[5 : 0] == 16;
assign W_op_br = W_iw_op[5 : 0] == 6;
assign W_op_ldh = W_iw_op[5 : 0] == 15;
assign W_op_initi = W_op_opx & (W_iw_opx[5 : 0] == 41);
assign W_op_roli = W_op_opx & (W_iw_opx[5 : 0] == 2);
assign W_op_cmpne = W_op_opx & (W_iw_opx[5 : 0] == 24);
assign W_op_nor = W_op_opx & (W_iw_opx[5 : 0] == 6);
assign W_op_trap = W_op_opx & (W_iw_opx[5 : 0] == 45);
assign W_op_sll = W_op_opx & (W_iw_opx[5 : 0] == 19);
assign W_op_sra = W_op_opx & (W_iw_opx[5 : 0] == 59);
assign W_op_cmpltu = W_op_opx & (W_iw_opx[5 : 0] == 48);
assign W_op_wrctl = W_op_opx & (W_iw_opx[5 : 0] == 46);
assign W_op_bret = W_op_opx & (W_iw_opx[5 : 0] == 9);
assign W_op_rol = W_op_opx & (W_iw_opx[5 : 0] == 3);
assign W_op_and = W_op_opx & (W_iw_opx[5 : 0] == 14);
assign W_op_rsvx00 = W_op_opx & (W_iw_opx[5 : 0] == 0);
assign W_op_rsvx20 = W_op_opx & (W_iw_opx[5 : 0] == 20);
assign W_op_cmplt = W_op_opx & (W_iw_opx[5 : 0] == 16);
assign W_op_ror = W_op_opx & (W_iw_opx[5 : 0] == 11);
assign W_op_hbreak = W_op_opx & (W_iw_opx[5 : 0] == 53);
assign W_op_callr = W_op_opx & (W_iw_opx[5 : 0] == 29);
assign W_op_rsvx21 = W_op_opx & (W_iw_opx[5 : 0] == 21);
assign W_op_srl = W_op_opx & (W_iw_opx[5 : 0] == 27);
assign W_op_intr = W_op_opx & (W_iw_opx[5 : 0] == 61);
assign W_op_rsvx25 = W_op_opx & (W_iw_opx[5 : 0] == 25);
assign W_op_eret = W_op_opx & (W_iw_opx[5 : 0] == 1);
assign W_op_rsvx42 = W_op_opx & (W_iw_opx[5 : 0] == 42);
assign W_op_cmpge = W_op_opx & (W_iw_opx[5 : 0] == 8);
assign W_op_rsvx43 = W_op_opx & (W_iw_opx[5 : 0] == 43);
assign W_op_rsvx60 = W_op_opx & (W_iw_opx[5 : 0] == 60);
assign W_op_rsvx44 = W_op_opx & (W_iw_opx[5 : 0] == 44);
assign W_op_divu = W_op_opx & (W_iw_opx[5 : 0] == 36);
assign W_op_rsvx62 = W_op_opx & (W_iw_opx[5 : 0] == 62);
assign W_op_flushi = W_op_opx & (W_iw_opx[5 : 0] == 12);
assign W_op_rsvx63 = W_op_opx & (W_iw_opx[5 : 0] == 63);
assign W_op_rsvx47 = W_op_opx & (W_iw_opx[5 : 0] == 47);
assign W_op_cmpgeu = W_op_opx & (W_iw_opx[5 : 0] == 40);
assign W_op_mulxss = W_op_opx & (W_iw_opx[5 : 0] == 31);
assign W_op_break = W_op_opx & (W_iw_opx[5 : 0] == 52);
assign W_op_div = W_op_opx & (W_iw_opx[5 : 0] == 37);
assign W_op_cmpeq = W_op_opx & (W_iw_opx[5 : 0] == 32);
assign W_op_slli = W_op_opx & (W_iw_opx[5 : 0] == 18);
assign W_op_mulxsu = W_op_opx & (W_iw_opx[5 : 0] == 23);
assign W_op_nextpc = W_op_opx & (W_iw_opx[5 : 0] == 28);
assign W_op_flushp = W_op_opx & (W_iw_opx[5 : 0] == 4);
assign W_op_xor = W_op_opx & (W_iw_opx[5 : 0] == 30);
assign W_op_sync = W_op_opx & (W_iw_opx[5 : 0] == 54);
assign W_op_mulxuu = W_op_opx & (W_iw_opx[5 : 0] == 7);
assign W_op_mul = W_op_opx & (W_iw_opx[5 : 0] == 39);
assign W_op_rsvx10 = W_op_opx & (W_iw_opx[5 : 0] == 10);
assign W_op_sub = W_op_opx & (W_iw_opx[5 : 0] == 57);
assign W_op_srli = W_op_opx & (W_iw_opx[5 : 0] == 26);
assign W_op_jmp = W_op_opx & (W_iw_opx[5 : 0] == 13);
assign W_op_rsvx15 = W_op_opx & (W_iw_opx[5 : 0] == 15);
assign W_op_rsvx33 = W_op_opx & (W_iw_opx[5 : 0] == 33);
assign W_op_rsvx17 = W_op_opx & (W_iw_opx[5 : 0] == 17);
assign W_op_rsvx50 = W_op_opx & (W_iw_opx[5 : 0] == 50);
assign W_op_rsvx34 = W_op_opx & (W_iw_opx[5 : 0] == 34);
assign W_op_rsvx51 = W_op_opx & (W_iw_opx[5 : 0] == 51);
assign W_op_rdctl = W_op_opx & (W_iw_opx[5 : 0] == 38);
assign W_op_rsvx35 = W_op_opx & (W_iw_opx[5 : 0] == 35);
assign W_op_or = W_op_opx & (W_iw_opx[5 : 0] == 22);
assign W_op_add = W_op_opx & (W_iw_opx[5 : 0] == 49);
assign W_op_srai = W_op_opx & (W_iw_opx[5 : 0] == 58);
assign W_op_rsvx55 = W_op_opx & (W_iw_opx[5 : 0] == 55);
assign W_op_rsvx56 = W_op_opx & (W_iw_opx[5 : 0] == 56);
assign W_op_ret = W_op_opx & (W_iw_opx[5 : 0] == 5);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign M_wr_data_unfiltered_0_is_x = ^(M_wr_data_unfiltered[0]) === 1'bx;
assign M_wr_data_filtered[0] = (M_wr_data_unfiltered_0_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[0];
assign M_wr_data_unfiltered_1_is_x = ^(M_wr_data_unfiltered[1]) === 1'bx;
assign M_wr_data_filtered[1] = (M_wr_data_unfiltered_1_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[1];
assign M_wr_data_unfiltered_2_is_x = ^(M_wr_data_unfiltered[2]) === 1'bx;
assign M_wr_data_filtered[2] = (M_wr_data_unfiltered_2_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[2];
assign M_wr_data_unfiltered_3_is_x = ^(M_wr_data_unfiltered[3]) === 1'bx;
assign M_wr_data_filtered[3] = (M_wr_data_unfiltered_3_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[3];
assign M_wr_data_unfiltered_4_is_x = ^(M_wr_data_unfiltered[4]) === 1'bx;
assign M_wr_data_filtered[4] = (M_wr_data_unfiltered_4_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[4];
assign M_wr_data_unfiltered_5_is_x = ^(M_wr_data_unfiltered[5]) === 1'bx;
assign M_wr_data_filtered[5] = (M_wr_data_unfiltered_5_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[5];
assign M_wr_data_unfiltered_6_is_x = ^(M_wr_data_unfiltered[6]) === 1'bx;
assign M_wr_data_filtered[6] = (M_wr_data_unfiltered_6_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[6];
assign M_wr_data_unfiltered_7_is_x = ^(M_wr_data_unfiltered[7]) === 1'bx;
assign M_wr_data_filtered[7] = (M_wr_data_unfiltered_7_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[7];
assign M_wr_data_unfiltered_8_is_x = ^(M_wr_data_unfiltered[8]) === 1'bx;
assign M_wr_data_filtered[8] = (M_wr_data_unfiltered_8_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[8];
assign M_wr_data_unfiltered_9_is_x = ^(M_wr_data_unfiltered[9]) === 1'bx;
assign M_wr_data_filtered[9] = (M_wr_data_unfiltered_9_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[9];
assign M_wr_data_unfiltered_10_is_x = ^(M_wr_data_unfiltered[10]) === 1'bx;
assign M_wr_data_filtered[10] = (M_wr_data_unfiltered_10_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[10];
assign M_wr_data_unfiltered_11_is_x = ^(M_wr_data_unfiltered[11]) === 1'bx;
assign M_wr_data_filtered[11] = (M_wr_data_unfiltered_11_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[11];
assign M_wr_data_unfiltered_12_is_x = ^(M_wr_data_unfiltered[12]) === 1'bx;
assign M_wr_data_filtered[12] = (M_wr_data_unfiltered_12_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[12];
assign M_wr_data_unfiltered_13_is_x = ^(M_wr_data_unfiltered[13]) === 1'bx;
assign M_wr_data_filtered[13] = (M_wr_data_unfiltered_13_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[13];
assign M_wr_data_unfiltered_14_is_x = ^(M_wr_data_unfiltered[14]) === 1'bx;
assign M_wr_data_filtered[14] = (M_wr_data_unfiltered_14_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[14];
assign M_wr_data_unfiltered_15_is_x = ^(M_wr_data_unfiltered[15]) === 1'bx;
assign M_wr_data_filtered[15] = (M_wr_data_unfiltered_15_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[15];
assign M_wr_data_unfiltered_16_is_x = ^(M_wr_data_unfiltered[16]) === 1'bx;
assign M_wr_data_filtered[16] = (M_wr_data_unfiltered_16_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[16];
assign M_wr_data_unfiltered_17_is_x = ^(M_wr_data_unfiltered[17]) === 1'bx;
assign M_wr_data_filtered[17] = (M_wr_data_unfiltered_17_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[17];
assign M_wr_data_unfiltered_18_is_x = ^(M_wr_data_unfiltered[18]) === 1'bx;
assign M_wr_data_filtered[18] = (M_wr_data_unfiltered_18_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[18];
assign M_wr_data_unfiltered_19_is_x = ^(M_wr_data_unfiltered[19]) === 1'bx;
assign M_wr_data_filtered[19] = (M_wr_data_unfiltered_19_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[19];
assign M_wr_data_unfiltered_20_is_x = ^(M_wr_data_unfiltered[20]) === 1'bx;
assign M_wr_data_filtered[20] = (M_wr_data_unfiltered_20_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[20];
assign M_wr_data_unfiltered_21_is_x = ^(M_wr_data_unfiltered[21]) === 1'bx;
assign M_wr_data_filtered[21] = (M_wr_data_unfiltered_21_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[21];
assign M_wr_data_unfiltered_22_is_x = ^(M_wr_data_unfiltered[22]) === 1'bx;
assign M_wr_data_filtered[22] = (M_wr_data_unfiltered_22_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[22];
assign M_wr_data_unfiltered_23_is_x = ^(M_wr_data_unfiltered[23]) === 1'bx;
assign M_wr_data_filtered[23] = (M_wr_data_unfiltered_23_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[23];
assign M_wr_data_unfiltered_24_is_x = ^(M_wr_data_unfiltered[24]) === 1'bx;
assign M_wr_data_filtered[24] = (M_wr_data_unfiltered_24_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[24];
assign M_wr_data_unfiltered_25_is_x = ^(M_wr_data_unfiltered[25]) === 1'bx;
assign M_wr_data_filtered[25] = (M_wr_data_unfiltered_25_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[25];
assign M_wr_data_unfiltered_26_is_x = ^(M_wr_data_unfiltered[26]) === 1'bx;
assign M_wr_data_filtered[26] = (M_wr_data_unfiltered_26_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[26];
assign M_wr_data_unfiltered_27_is_x = ^(M_wr_data_unfiltered[27]) === 1'bx;
assign M_wr_data_filtered[27] = (M_wr_data_unfiltered_27_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[27];
assign M_wr_data_unfiltered_28_is_x = ^(M_wr_data_unfiltered[28]) === 1'bx;
assign M_wr_data_filtered[28] = (M_wr_data_unfiltered_28_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[28];
assign M_wr_data_unfiltered_29_is_x = ^(M_wr_data_unfiltered[29]) === 1'bx;
assign M_wr_data_filtered[29] = (M_wr_data_unfiltered_29_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[29];
assign M_wr_data_unfiltered_30_is_x = ^(M_wr_data_unfiltered[30]) === 1'bx;
assign M_wr_data_filtered[30] = (M_wr_data_unfiltered_30_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[30];
assign M_wr_data_unfiltered_31_is_x = ^(M_wr_data_unfiltered[31]) === 1'bx;
assign M_wr_data_filtered[31] = (M_wr_data_unfiltered_31_is_x & (M_ctrl_ld_non_io)) ? 1'b0 : M_wr_data_unfiltered[31];
always @(posedge clk)
begin
if (reset_n)
if (^(W_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: cpu_test_bench/W_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_wr_dst_reg)
if (^(W_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: cpu_test_bench/W_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: ERROR: cpu_test_bench/W_wr_data is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: cpu_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(W_pcb) === 1'bx)
begin
$write("%0d ns: ERROR: cpu_test_bench/W_pcb is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(W_iw) === 1'bx)
begin
$write("%0d ns: ERROR: cpu_test_bench/W_iw is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(M_en) === 1'bx)
begin
$write("%0d ns: ERROR: cpu_test_bench/M_en is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
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