sysid.v

这个是基于NIOS II的FPGA平台的一个CF卡的接口模块

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// synthesis translate_off
`timescale 1ns / 100ps
// synthesis translate_on
module sysid (
               // inputs:
                address,

               // outputs:
                readdata
             );

  output  [ 31: 0] readdata;
  input            address;

  wire    [ 31: 0] readdata;
  //control_slave, which is an e_avalon_slave
  assign readdata = address ? 1116009437 : 2375950459;


endmodule