📄 ddr_sdram.html
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</style></HEAD><BODY align=left style='background-color: #ffffff;'><DIV align=left><TABLE width=95% border=0 cellpadding=2><TR><TD><TABLE cellpadding=2 border=0 ><TR><WIZARD></WIZARD><TD><H1>Generation Report - DDR SDRAM Controller v3.2.0</H1></TD></TR></TABLE></TD></TR><TR><TD><TABLE cellpadding=2 border=1 width=60%><TR><TD><B>Entity Name</B></TD><TD>ddr_sdram_auk_ddr_sdram</TD></TR><TR><TD><B>Variation Name</B></TD><TD>ddr_sdram</TD></TR><TR><TD><B>Variation HDL</B></TD><TD>Verilog HDL</TD></TR><TR><TD><B>Output Directory</B></TD><TD>C:/designs/cf_tests/to_nios_forum/std_cf_2c35</TD></TR></TABLE></TD></TR><TR><TD><h2>File Summary</h2>IP Toolbench is creating the following files in the output directory:</TD></TR><TR><TD><TABLE cellspacing=2 cellpadding=2 border=1 width=100%><TR align=left><TH align=left align=top width=25%><B>File</B></TH><TH align=left><B>Description</B></TH></TR><TR><TD>ddr_sdram.v</TD><TD>A MegaCore<small><sup>®</sup></small> function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.</TD></TR><TR><TD>ddr_sdram_inst.v</TD><TD>Verilog HDL sample instantiation file</TD></TR><TR><TD>ddr_sdram.cmp</TD><TD>A VHDL component declaration for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore function.</TD></TR><TR><TD>ddr_sdram.inc</TD><TD>An AHDL include declaration file for the MegaCore function variation. Include this file with any AHDL architecture that instantiates the MegaCore function.</TD></TR><TR><TD>ddr_sdram_bb.v</TD><TD>Verilog HDL black-box file for the MegaCore function variation. Use this file when using a third-party EDA tool to synthesize your design.</TD></TR><TR><TD>ddr_sdram_auk_ddr_dqs_group.v</TD><TD>Design file containing the datapath byte groups.</TD></TR><TR><TD>ddr_sdram_auk_ddr_clk_gen.v</TD><TD>Design file containing the clock output generators.</TD></TR><TR><TD>ddr_sdram_auk_ddr_datapath.v</TD><TD>Design file that instantiates the byte groups and the clock output generators.</TD></TR><TR><TD>ddr_sdram_auk_ddr_sdram.v</TD><TD>Design file that instantiates the controller logic and the datapath.</TD></TR><TR><TD>ddr_sdram_debug_design.v</TD><TD> Example top-level design file.</TD></TR><TR><TD>ddr_sdram_debug_design_tb.v</TD><TD>Testbench for the example top level design file.</TD></TR><TR><TD>add_constraints_for_ddr_sdram.tcl</TD><TD>DDR constraints script.</TD></TR><TR><TD>verify_timing_for_ddr_sdram.tcl</TD><TD>Post-compilation timing analysis script.</TD></TR><TR><TD>altera_vhdl_support.vhd</TD><TD>VHDL support file.</TD></TR><TR><TD>ddr_sdram.html</TD><TD>The MegaCore function report file.</TD></TR></TABLE></TD></TR><TR><TD><h2>MegaCore Function Variation File Ports</h2><TABLE border=1 cellpadding=2 cellspacing=0 width=75%><TR align=left><TH align=left><B>Name</B></TH><TH align=left><B>Direction</B></TH><TH align=left><B>Width</B></TH></TR><TR><TD>clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>write_clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>reset_n</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>write_clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>local_read_req</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>local_write_req</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>local_addr</TD><TD>INPUT</TD><TD>23</TD></TR><TR><TD>local_wdata</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>local_be</TD><TD>INPUT</TD><TD>4</TD></TR><TR><TD>local_ready</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>local_rdata</TD><TD>OUTPUT</TD><TD>32</TD></TR><TR><TD>local_rdata_valid</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>clk_to_sdram</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>clk_to_sdram_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ddr_cs_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ddr_cke</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ddr_a</TD><TD>OUTPUT</TD><TD>13</TD></TR><TR><TD>ddr_ba</TD><TD>OUTPUT</TD><TD>2</TD></TR><TR><TD>ddr_ras_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ddr_cas_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ddr_we_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ddr_dq</TD><TD>BIDIR</TD><TD>16</TD></TR><TR><TD>ddr_dqs</TD><TD>BIDIR</TD><TD>2</TD></TR><TR><TD>ddr_dm</TD><TD>OUTPUT</TD><TD>2</TD></TR></TABLE></TD></TR></TD></TR></TABLE></DIV></BODY></HTML>⌨️ 快捷键说明
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