ddr_sdram_inst.v

这个是基于NIOS II的FPGA平台的一个CF卡的接口模块

// Generated by DDR SDRAM Controller 3.2.0 [Altera, IP Toolbench v1.2.9 build43]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2005 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera.  Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
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	ddr_sdram	ddr_sdram_inst(
		.clk(clk_sig),
		.write_clk(write_clk_sig),
		.reset_n(reset_n_sig),
		.local_read_req(local_read_req_sig),
		.local_write_req(local_write_req_sig),
		.local_addr(local_addr_sig),
		.local_wdata(local_wdata_sig),
		.local_be(local_be_sig),
		.local_ready(local_ready_sig),
		.local_rdata(local_rdata_sig),
		.local_rdata_valid(local_rdata_valid_sig),
		.clk_to_sdram(clk_to_sdram_sig),
		.clk_to_sdram_n(clk_to_sdram_n_sig),
		.ddr_cs_n(ddr_cs_n_sig),
		.ddr_cke(ddr_cke_sig),
		.ddr_a(ddr_a_sig),
		.ddr_ba(ddr_ba_sig),
		.ddr_ras_n(ddr_ras_n_sig),
		.ddr_cas_n(ddr_cas_n_sig),
		.ddr_we_n(ddr_we_n_sig),
		.ddr_dm(ddr_dm_sig),
		.ddr_dq(ddr_dq_sig),
		.ddr_dqs(ddr_dqs_sig));