ddr_sdram_post_summary.txt

这个是基于NIOS II的FPGA平台的一个CF卡的接口模块

NOTE:     Speed Grade c6 used for analysis
NOTE:     Memory device can operate at 85.00 MHz with a lower CL than 2.5
  
 DDR read data capture: DDR Data to DQS strobe edges at capture registers. 
             Setup slack is  1949 ps    associated with pin 'ddr_dq[1]'  ( variation port 'dq(9)', 'input_cell_H[0]')              
             Hold slack is   1492 ps    associated with pin 'ddr_dq[3]'  ( variation port 'dq(11)', 'input_cell_L[0]')              
  
 Read data resynchronisation: Captured data to resync clock at resync registers ('resynched_data').  
             Setup slack is  4682 ps    associated with pin 'ddr_dq[2]'  ( variation port 'dq(10)', 'input_cell_H[0]')                  
             Hold slack is    756 ps    associated with pin 'ddr_dq[4]'  ( variation port 'dq(12)', 'input_cell_H[0]')              
  
 Read Postamble Enable: Enable-release to DQS strobe postamble period at negative-edge capture registers.  
             Setup slack is  2000 ps    associated with pin 'ddr_dq[0]'  ( variation port 'dq(8)', 'input_cell_L[0]')                  
             Hold slack is guaranteed by design to always be positive for Cyclone II
  
 Read Postamble Control: Preset-release ('dq_enable_reset') to DQS strobe negative edges at postamble register ('dq_enable').       
             Setup slack is  4665 ps    associated with pin 'ddr_dq[0]'  ( variation port 'dq(8)', 'input_cell_L[0]')                  
             Hold slack is   3185 ps    associated with pin 'ddr_dq[4]'  ( variation port 'dq(4)', 'input_cell_L[0]')