ddr_sdram_debug_design_1.v

这个是基于NIOS II的FPGA平台的一个CF卡的接口模块

//Legal Notice: (C)2005 Altera Corporation. All rights reserved.  Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors.  Please refer to the applicable
//agreement for further details.

// synthesis translate_off
`timescale 1ps / 1ps
// synthesis translate_on
//------------------------------------------------------------------------------
//This confidential and proprietary software may be used only as authorized by
//a licensing agreement from Altera Corporation.
//(C) COPYRIGHT 2004 ALTERA CORPORATION
//ALL RIGHTS RESERVED
//The entire notice above must be reproduced on all authorized copies and any
//such reproduction must be pursuant to a licensing agreement from Altera.
//Title        : Datapath for the Altera DDR SDRAM Controller
//Project      : DDR SDRAM Controller
//File         : ddr_sdram_ddr_dqs_group.v
//Revision     : V3.2.0
//Abstract:
//Automatically generated 'Example' top level design to allow compilation
//of your DDR SDRAM Controller instance in Quartus.
//This module instantiates your configured Altera DDR SDRAM Controller,
//some example driver logic, and a suitably configured PLL and DLL (where needed).
//------------------------------------------------------------------------------
//*************** This is a MegaWizard generated file ****************
//Altera strongly recommends that you use this file as the starting point of your
//own project top level. This is because the IP Toolbench wizard parses this file
//to update parameters or generics, pin prefixes and other settings to match any
//changes you make in the wizard. The wizard will only update sections of code
//between its special tags so it is safe to edit this file and add your own logic
//to it. This is the recommended design flow for using the megacore.
//If you create your own top level or remove the tags, then you must make sure that
//any changes you make in the wizard are also applied to this file.
//Whilst editing this file make sure the edits are not inside any 'MEGAWIZARD'
//text insertion areas.
//(between <<START MEGAWIZARD INSERT and<<END MEGAWIZARD INSERT comments)
//Any edits inside these delimiters will be overwritten by the megawizard if you
//re-run it.
//If you really need to make changes inside these delimiters then delete
//both 'START' and 'END' delimiters.  This will stop the megawizard updating this
//section again.
//----------------------------------------------------------------------------------
//<< START MEGAWIZARD INSERT PARAMETER_LIST
//Parameters:
//Device Family                      : Cyclone II
//local Interface Data Width         : 32
//DQ_PER_DQS                         : 8
//LOCAL_AVALON_IF                    : true
//MEM_CHIPSELS                       : 1
//MEM_CHIP_BITS                      : 0
//MEM_BANK_BITS                      : 2
//MEM_ROW_BITS                       : 13
//MEM_COL_BITS                       : 9
//LOCAL_BURST_LEN                    : 1
//LOCAL_BURST_LEN_BITS               : 1
//Number Of Output Clock Pairs       : 1
//<< END MEGAWIZARD INSERT PARAMETER_LIST
//----------------------------------------------------------------------------------
//<< MEGAWIZARD PARSE FILE DDR3.2.0
//<< START MEGAWIZARD INSERT MODULE

module ddr_sdram_debug_design (
                                // inputs:
                                 clock_source,
                                 reset_n,

                                // outputs:
                                 clk_to_sdram,
                                 clk_to_sdram_n,
                                 ddr_a,
                                 ddr_ba,
                                 ddr_cas_n,
                                 ddr_cke,
                                 ddr_cs_n,
                                 ddr_dm,
                                 ddr_dq,
                                 ddr_dqs,
                                 ddr_ras_n,
                                 ddr_we_n,
                                 pnf,
                                 pnf_per_byte,
                                 test_complete
                              );

  output  [  0: 0] clk_to_sdram;
  output  [  0: 0] clk_to_sdram_n;
  output  [ 12: 0] ddr_a;
  output  [  1: 0] ddr_ba;
  output           ddr_cas_n;
  output  [  0: 0] ddr_cke;
  output  [  0: 0] ddr_cs_n;
  output  [  1: 0] ddr_dm;
  inout   [ 15: 0] ddr_dq;
  inout   [  1: 0] ddr_dqs;
  output           ddr_ras_n;
  output           ddr_we_n;
  output           pnf;
  output  [  3: 0] pnf_per_byte;
  output           test_complete;
  input            clock_source;
  input            reset_n;

  wire             clk;
  wire    [  0: 0] clk_to_sdram;
  wire    [  0: 0] clk_to_sdram_n;
  wire    [ 12: 0] ddr_a;
  wire    [  1: 0] ddr_ba;
  wire             ddr_cas_n;
  wire    [  0: 0] ddr_cke;
  wire    [  0: 0] ddr_cs_n;
  wire    [  1: 0] ddr_dm;
  wire    [ 15: 0] ddr_dq;
  wire    [  1: 0] ddr_dqs;
  wire    [ 22: 0] ddr_local_addr;
  wire    [  3: 0] ddr_local_be;
  wire    [  8: 0] ddr_local_col_addr;
  wire             ddr_local_cs_addr;
  wire    [ 31: 0] ddr_local_rdata;
  wire             ddr_local_rdata_valid;
  wire             ddr_local_read_req;
  wire             ddr_local_ready;
  wire             ddr_local_refresh_req;
  wire             ddr_local_size;
  wire    [ 31: 0] ddr_local_wdata;
  wire             ddr_local_write_req;
  wire             ddr_ras_n;
  wire             ddr_we_n;
  wire             dedicated_resynch_or_capture_clk;
  wire             pnf;
  wire    [  3: 0] pnf_per_byte;
  wire             test_complete;
  wire             write_clk;
  //<< END MEGAWIZARD INSERT MODULE
  //<< START MEGAWIZARD INSERT REFRESH_REQ
  // Custom logic to implement user controlled refreshes can be added here....
  // refreshes disabled
  assign ddr_local_refresh_req = 1'b0;

  //<< END MEGAWIZARD INSERT REFRESH_REQ
  //<< START MEGAWIZARD INSERT WRAPPER_NAME
  ddr_sdram ddr_sdram_ddr_sdram
    (
      .clk (clk),
      .clk_to_sdram (clk_to_sdram),
      .clk_to_sdram_n (clk_to_sdram_n),
      .ddr_a (ddr_a),
      .ddr_ba (ddr_ba),
      .ddr_cas_n (ddr_cas_n),
      .ddr_cke (ddr_cke),
      .ddr_cs_n (ddr_cs_n),
      .ddr_dm (ddr_dm[1 : 0]),
      .ddr_dq (ddr_dq),
      .ddr_dqs (ddr_dqs[1 : 0]),
      .ddr_ras_n (ddr_ras_n),
      .ddr_we_n (ddr_we_n),
      .local_addr (ddr_local_addr),
      .local_be (ddr_local_be),
      .local_rdata (ddr_local_rdata),
      .local_rdata_valid (ddr_local_rdata_valid),
      .local_read_req (ddr_local_read_req),
      .local_ready (ddr_local_ready),
      .local_wdata (ddr_local_wdata),
      .local_write_req (ddr_local_write_req),
      .reset_n (reset_n),
      .write_clk (write_clk)
    );


  //<< END MEGAWIZARD INSERT WRAPPER_NAME
  //<< START MEGAWIZARD INSERT CS_ADDR_MAP
  //connect up the column address bits
  assign ddr_local_addr[7 : 0] = ddr_local_col_addr[8 : 1];

  //<< END MEGAWIZARD INSERT CS_ADDR_MAP
  //

  //<< START MEGAWIZARD INSERT EXAMPLE_DRIVER
  //<<Self-test, synthesisable code to exercise the DDR SDRAM Controller
  ddr_sdram_example_driver driver
    (
      .clk (clk),
      .local_bank_addr (ddr_local_addr[22 : 21]),
      .local_be (ddr_local_be),
      .local_col_addr (ddr_local_col_addr),
      .local_cs_addr (ddr_local_cs_addr),
      .local_rdata (ddr_local_rdata),
      .local_rdata_valid (ddr_local_rdata_valid),
      .local_read_req (ddr_local_read_req),
      .local_ready (ddr_local_ready),
      .local_row_addr (ddr_local_addr[20 : 8]),
      .local_size (ddr_local_size),
      .local_wdata (ddr_local_wdata),
      .local_write_req (ddr_local_write_req),
      .pnf_per_byte (pnf_per_byte),
      .pnf_persist (pnf),
      .reset_n (reset_n),
      .test_complete (test_complete)
    );

  defparam driver.AVALON_IF = "true",
           driver.LOCAL_BURST_LEN = 1,
           driver.LOCAL_BURST_LEN_BITS = 1,
           driver.LOCAL_DATA_BITS = 32,
           driver.MEM_BANK_BITS = 2,
           driver.MEM_CHIPSELS = 1,
           driver.MEM_CHIP_BITS = 0,
           driver.MEM_COL_BITS = 9,
           driver.MEM_DQ_PER_DQS = 8,
           driver.MEM_ROW_BITS = 13;

  //<< END MEGAWIZARD INSERT EXAMPLE_DRIVER
  //<< START MEGAWIZARD INSERT PLL
  ddr_pll_cycloneii g_cyclonepll_ddr_pll_inst
    (
      .c0 (clk),
      .c1 (write_clk),
      .c2 (dedicated_resynch_or_capture_clk),
      .inclk0 (clock_source)
    );


  //<< END MEGAWIZARD INSERT PLL

  //<< START MEGAWIZARD INSERT DLL

  //<< END MEGAWIZARD INSERT DLL

  //<< start europa


endmodule