ddr_sdram_debug_design_tb_1.v

这个是基于NIOS II的FPGA平台的一个CF卡的接口模块

    assign ras_n_delayed = ras_n ;
    assign cas_n_delayed = cas_n ;
    assign we_n_delayed = we_n ;
    assign dm_delayed = dm ;

    // ---------------------------------------------------------------
    initial
    begin : endit
        integer count;
        reg ln;
        count = 0;

        // Stop simulation after test_complete or TINIT + 2000 clocks
        while ((count < (TINIT_CLOCKS + 2000)) & (test_complete !== 1))
        begin
            count = count + 1;
            @(negedge clk_to_sdram[0]);
        end
        if (test_complete === 1)
        begin
            if (pnf)
            begin
                $write($time);
                $write("          --- SIMULATION PASSED --- ");
                $stop;
            end
            else
            begin
                $write($time);
                $write("          --- SIMULATION FAILED --- ");
                $stop;
            end
        end
        else
        begin
            $write($time);
            $write("          --- SIMULATION FAILED, DID NOT COMPLETE --- ");
            $stop;
        end
    end

    always @(clk_to_sdram[0] or reset_n)
    begin
        if (!reset_n)
        begin
            test_complete_count <= 0 ;
        end
        else if ((clk_to_sdram[0]))
        begin
            if (test_complete)
            begin
                test_complete_count <= test_complete_count + 1 ;
            end
        end
    end


    assign #((GATE_BOARD_DQS_DELAY) + 1) fpga_dq_int = (dq_oe) ? mem_dq : all_dq_z;   // This is effectively the read dir so it should have 90 deg added

    assign                  fpga_dq_int0 = fpga_dq_int;
    assign #(D90_DEG_DELAY) fpga_dq_int1 = fpga_dq_int;
    assign #(D90_DEG_DELAY) fpga_dq_int2 = fpga_dq_int1;
    assign #(D90_DEG_DELAY) fpga_dq_int3 = fpga_dq_int2;
    assign #(D90_DEG_DELAY) fpga_dq_int4 = fpga_dq_int3;
    assign #(D90_DEG_DELAY) fpga_dq_int5 = fpga_dq_int4;
    assign #(D90_DEG_DELAY) fpga_dq_int6 = fpga_dq_int5;
    assign #(D90_DEG_DELAY) fpga_dq_int7 = fpga_dq_int6;

    // << START MEGAWIZARD INSERT DQ_DELAYS
    assign fpga_dq = RTL_DELAYS ? fpga_dq_int4 : fpga_dq_int;
    // << END MEGAWIZARD INSERT DQ_DELAYS



    assign #((GATE_BOARD_DQS_DELAY * 1 + 1)) mem_dq = (~dq_oe) ? fpga_dq: all_dq_z;

    always@(mem_dq or fpga_dq or dq_active)
    begin
        if ((mem_dq !== all_dq_z) && (dq_active == 1'b0) )
        begin
            dq_active = 1'b1;
            dq_oe = 1'b1;
        end

        if ((fpga_dq !== all_dq_z) && (dq_active == 1'b0))
        begin
            dq_active = 1'b1;
            dq_oe = 1'b0;
        end

        if ((mem_dq === all_dq_z) && (fpga_dq === all_dq_z))
        begin
            dq_active = 1'b0;
        end
    end




    assign #(GATE_BOARD_DQS_DELAY + 1) fpga_dqs_int = (dqs_oe) ? mem_dqs : all_dqs_z;   // This is effectively the read dir so it should have 90 deg added

    assign                  fpga_dqs_int0 = fpga_dqs_int;
    assign #(D90_DEG_DELAY) fpga_dqs_int1 = fpga_dqs_int;
    assign #(D90_DEG_DELAY) fpga_dqs_int2 = fpga_dqs_int1;
    assign #(D90_DEG_DELAY) fpga_dqs_int3 = fpga_dqs_int2;
    assign #(D90_DEG_DELAY) fpga_dqs_int4 = fpga_dqs_int3;
    assign #(D90_DEG_DELAY) fpga_dqs_int5 = fpga_dqs_int4;
    assign #(D90_DEG_DELAY) fpga_dqs_int6 = fpga_dqs_int5;
    assign #(D90_DEG_DELAY) fpga_dqs_int7 = fpga_dqs_int6;

    // << START MEGAWIZARD INSERT DQS_DELAYS
    assign fpga_dqs = RTL_DELAYS ? fpga_dqs_int4 : fpga_dqs_int;
    // << END MEGAWIZARD INSERT DQS_DELAYS



    assign #(((GATE_BOARD_DQS_DELAY)) * 1 + 1) mem_dqs = (~dqs_oe) ? fpga_dqs: all_dqs_z;

    always@(mem_dqs or fpga_dqs or dqs_active)
    begin
        if ((mem_dqs !== all_dqs_z) && (dqs_active == 1'b0) )
        begin
            dqs_active = 1'b1;
            dqs_oe = 1'b1;
        end

        if ((fpga_dqs !== all_dqs_z) && (dqs_active == 1'b0))
        begin
            dqs_active = 1'b1;
            dqs_oe = 1'b0;
        end

        if ((mem_dqs === all_dqs_z) && (fpga_dqs === all_dqs_z))
        begin
            dqs_active = 1'b0;
        end
    end


    reg[2:0] cmd_bus;
    reg ln_;


    //******************************* DQS ****************************
    // Watch the SDRAM command bus
    always @(clk_to_ram)
    begin
        if (clk_to_ram)
        begin
            if (1'b1)
            begin
                cmd_bus = {ras_n_delayed, cas_n_delayed, we_n_delayed};
                case (cmd_bus)
                    3'b000 :
                        begin
                            // LMR command
                            $write($time);
                            if (ba_delayed == zero_one)
                            begin
                                $write("          ELMR     settings = ");
                                if (!(a_delayed[0]))
                                begin
                                    $write("DLL enable");
                                end
                            end
                            else
                            begin
                                $write("          LMR      settings = ");
                                case (a_delayed[2:0])
                                    3'b001 :
                                        begin
                                            $write("BL = 2,");
                                        end
                                    3'b010 :
                                        begin
                                            $write("BL = 4,");
                                        end
                                    3'b011 :
                                        begin
                                            $write("BL = 8,");
                                        end
                                    default :
                                        begin
                                            $write("BL = ??,");
                                        end
                                endcase
                                case (a_delayed[6:4])
                                    3'b010 :
                                        begin
                                            $write(" CL = 2.0,");
                                        end
                                    3'b110 :
                                        begin
                                            $write(" CL = 2.5,");
                                        end
                                    3'b011 :
                                        begin
                                            $write(" CL = 3.0,");
                                        end
                                    3'b100 :
                                        begin
                                            $write(" CL = 4.0,");
                                        end
                                    3'b101 :
                                        begin
                                            $write(" CL = 5.0,");
                                        end
                                    default :
                                        begin
                                            $write(" CL = ??,");
                                        end
                                endcase
                                if ((a_delayed[8]))
                                begin
                                    $write(" DLL reset");
                                end
                            end
                            $write("\n");
                        end
                    3'b001 :
                        begin
                            // ARF command
                            $write($time);
                            $write("          ARF\n");
                        end
                    3'b010 :
                        begin
                            // PCH command
                            $write($time);
                            $write("          PCH");
                            if ((a_delayed[10]))
                            begin
                                $write(" all banks \n");
                            end
                            else
                            begin
                                $write(" bank ");
                                $write("%H\n", ba_delayed);
                            end
                        end
                    3'b011 :
                        begin
                            // ACT command
                            $write($time);
                            $write("          ACT     row address ");
                            $write("%H", a_delayed);
                            $write(" bank ");
                            $write("%H\n", ba_delayed);
                        end
                   3'b100 :
                        begin
                            // WR command
                            $write($time);
                            $write("          WR to   col address ");
                            $write("%H", a_delayed);
                            $write(" bank ");
                            $write("%H\n", ba_delayed);
                        end
                   3'b101 :
                        begin
                            // RD command
                            $write($time);
                            $write("          RD from col address ");
                            $write("%H", a_delayed);
                            $write(" bank ");
                            $write("%H\n", ba_delayed);
                        end
                   3'b110 :
                        begin
                            // BT command
                            $write($time);
                            $write("          BT ");
                        end
                   3'b111 :
                        begin
                            // NOP command
                        end
                endcase
            end
            else
            begin
            end // if enabled
        end
    end

endmodule