std_2c35.v

这个是基于NIOS II的FPGA平台的一个CF卡的接口模块

                            cpu_data_master_writedata,
                            reset_n,

                           // outputs:
                            cf_ctl_address,
                            cf_ctl_chipselect_n,
                            cf_ctl_irq_from_sa,
                            cf_ctl_read_n,
                            cf_ctl_readdata_from_sa,
                            cf_ctl_reset_n,
                            cf_ctl_wait_counter_eq_0,
                            cf_ctl_wait_counter_eq_1,
                            cf_ctl_write_n,
                            cf_ctl_writedata,
                            cpu_data_master_granted_cf_ctl,
                            cpu_data_master_qualified_request_cf_ctl,
                            cpu_data_master_read_data_valid_cf_ctl,
                            cpu_data_master_requests_cf_ctl,
                            d1_cf_ctl_end_xfer
                         );

  output  [  1: 0] cf_ctl_address;
  output           cf_ctl_chipselect_n;
  output           cf_ctl_irq_from_sa;
  output           cf_ctl_read_n;
  output  [ 31: 0] cf_ctl_readdata_from_sa;
  output           cf_ctl_reset_n;
  output           cf_ctl_wait_counter_eq_0;
  output           cf_ctl_wait_counter_eq_1;
  output           cf_ctl_write_n;
  output  [ 31: 0] cf_ctl_writedata;
  output           cpu_data_master_granted_cf_ctl;
  output           cpu_data_master_qualified_request_cf_ctl;
  output           cpu_data_master_read_data_valid_cf_ctl;
  output           cpu_data_master_requests_cf_ctl;
  output           d1_cf_ctl_end_xfer;
  input            cf_ctl_irq;
  input   [  3: 0] cf_ctl_readdata;
  input            clk;
  input   [ 26: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] cf_ctl_address;
  wire             cf_ctl_allgrants;
  wire             cf_ctl_allow_new_arb_cycle;
  wire             cf_ctl_any_continuerequest;
  wire             cf_ctl_arb_counter_enable;
  reg     [  2: 0] cf_ctl_arb_share_counter;
  wire    [  2: 0] cf_ctl_arb_share_counter_next_value;
  wire    [  2: 0] cf_ctl_arb_share_set_values;
  wire             cf_ctl_arbitration_holdoff_internal;
  wire             cf_ctl_beginbursttransfer_internal;
  wire             cf_ctl_begins_xfer;
  wire             cf_ctl_chipselect_n;
  wire    [  1: 0] cf_ctl_counter_load_value;
  wire             cf_ctl_end_xfer;
  wire             cf_ctl_firsttransfer;
  wire             cf_ctl_grant_vector;
  wire             cf_ctl_in_a_read_cycle;
  wire             cf_ctl_in_a_write_cycle;
  wire             cf_ctl_irq_from_sa;
  wire             cf_ctl_master_qreq_vector;
  wire             cf_ctl_read_n;
  wire    [ 31: 0] cf_ctl_readdata_from_sa;
  wire             cf_ctl_reset_n;
  reg              cf_ctl_slavearbiterlockenable;
  reg     [  1: 0] cf_ctl_wait_counter;
  wire             cf_ctl_wait_counter_eq_0;
  wire             cf_ctl_wait_counter_eq_1;
  wire             cf_ctl_waits_for_read;
  wire             cf_ctl_waits_for_write;
  wire             cf_ctl_write_n;
  wire    [ 31: 0] cf_ctl_writedata;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_cf_ctl;
  wire             cpu_data_master_qualified_request_cf_ctl;
  wire             cpu_data_master_read_data_valid_cf_ctl;
  wire             cpu_data_master_requests_cf_ctl;
  wire             cpu_data_master_saved_grant_cf_ctl;
  reg              d1_cf_ctl_end_xfer;
  reg              d1_reasons_to_wait;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             wait_for_cf_ctl_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~cf_ctl_end_xfer;
    end


  assign cf_ctl_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_cf_ctl));
  assign cpu_data_master_requests_cf_ctl = ({cpu_data_master_address_to_slave[26 : 4] , 4'b0} == 27'h1000040) & (cpu_data_master_read | cpu_data_master_write);
  //assign cf_ctl_readdata_from_sa = cf_ctl_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cf_ctl_readdata_from_sa = cf_ctl_readdata;

  //cf_ctl_arb_share_counter set values, which is an e_mux
  assign cf_ctl_arb_share_set_values = 1;

  //cf_ctl_arb_share_counter_next_value assignment, which is an e_assign
  assign cf_ctl_arb_share_counter_next_value = cf_ctl_firsttransfer ? (cf_ctl_arb_share_set_values - 1) : |cf_ctl_arb_share_counter ? (cf_ctl_arb_share_counter - 1) : 0;

  //cf_ctl_allgrants all slave grants, which is an e_mux
  assign cf_ctl_allgrants = |cf_ctl_grant_vector;

  //cf_ctl_end_xfer assignment, which is an e_assign
  assign cf_ctl_end_xfer = ~(cf_ctl_waits_for_read | cf_ctl_waits_for_write);

  //cf_ctl_arb_share_counter arbitration counter enable, which is an e_assign
  assign cf_ctl_arb_counter_enable = cf_ctl_end_xfer & cf_ctl_allgrants;

  //cf_ctl_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cf_ctl_arb_share_counter <= 0;
      else if (cf_ctl_arb_counter_enable)
          cf_ctl_arb_share_counter <= cf_ctl_arb_share_counter_next_value;
    end


  //cf_ctl_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cf_ctl_slavearbiterlockenable <= 0;
      else if (|cf_ctl_master_qreq_vector & cf_ctl_end_xfer)
          cf_ctl_slavearbiterlockenable <= |cf_ctl_arb_share_counter_next_value;
    end


  //cpu/data_master cf/ctl arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = cf_ctl_slavearbiterlockenable & cpu_data_master_continuerequest;

  //cf_ctl_any_continuerequest at least one master continues requesting, which is an e_assign
  assign cf_ctl_any_continuerequest = 0;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 0;

  assign cpu_data_master_qualified_request_cf_ctl = cpu_data_master_requests_cf_ctl;
  //cf_ctl_writedata mux, which is an e_mux
  assign cf_ctl_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_cf_ctl = cpu_data_master_qualified_request_cf_ctl;

  //cpu/data_master saved-grant cf/ctl, which is an e_assign
  assign cpu_data_master_saved_grant_cf_ctl = cpu_data_master_requests_cf_ctl;

  //allow new arb cycle for cf/ctl, which is an e_assign
  assign cf_ctl_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign cf_ctl_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign cf_ctl_master_qreq_vector = 1;

  //cf_ctl_reset_n assignment, which is an e_assign
  assign cf_ctl_reset_n = reset_n;

  assign cf_ctl_chipselect_n = ~cpu_data_master_granted_cf_ctl;
  //cf_ctl_firsttransfer first transaction, which is an e_assign
  assign cf_ctl_firsttransfer = ~(cf_ctl_slavearbiterlockenable & cf_ctl_any_continuerequest);

  //cf_ctl_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign cf_ctl_beginbursttransfer_internal = cf_ctl_begins_xfer & cf_ctl_firsttransfer;

  //cf_ctl_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign cf_ctl_arbitration_holdoff_internal = cf_ctl_begins_xfer & cf_ctl_firsttransfer;

  //~cf_ctl_read_n assignment, which is an e_mux
  assign cf_ctl_read_n = ~(((cpu_data_master_granted_cf_ctl & cpu_data_master_read))& ~cf_ctl_begins_xfer);

  //~cf_ctl_write_n assignment, which is an e_mux
  assign cf_ctl_write_n = ~(((cpu_data_master_granted_cf_ctl & cpu_data_master_write)) & ~cf_ctl_begins_xfer & (cf_ctl_wait_counter >= 1));

  //cf_ctl_address mux, which is an e_mux
  assign cf_ctl_address = cpu_data_master_address_to_slave >> 2;

  //d1_cf_ctl_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_cf_ctl_end_xfer <= 1;
      else if (1)
          d1_cf_ctl_end_xfer <= cf_ctl_end_xfer;
    end


  //cf_ctl_waits_for_read in a cycle, which is an e_mux
  assign cf_ctl_waits_for_read = cf_ctl_in_a_read_cycle & wait_for_cf_ctl_counter;

  //cf_ctl_in_a_read_cycle assignment, which is an e_assign
  assign cf_ctl_in_a_read_cycle = cpu_data_master_granted_cf_ctl & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = cf_ctl_in_a_read_cycle;

  //cf_ctl_wait_counter_eq_1 assignment, which is an e_assign
  assign cf_ctl_wait_counter_eq_1 = cf_ctl_wait_counter == 1;

  //cf_ctl_waits_for_write in a cycle, which is an e_mux
  assign cf_ctl_waits_for_write = cf_ctl_in_a_write_cycle & wait_for_cf_ctl_counter;

  //cf_ctl_in_a_write_cycle assignment, which is an e_assign
  assign cf_ctl_in_a_write_cycle = cpu_data_master_granted_cf_ctl & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = cf_ctl_in_a_write_cycle;

  assign cf_ctl_wait_counter_eq_0 = cf_ctl_wait_counter == 0;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cf_ctl_wait_counter <= 0;
      else if (1)
          cf_ctl_wait_counter <= cf_ctl_counter_load_value;
    end


  assign cf_ctl_counter_load_value = ((cf_ctl_in_a_write_cycle & cf_ctl_begins_xfer))? 2 :
    ((cf_ctl_in_a_read_cycle & cf_ctl_begins_xfer))? 1 :
    (~cf_ctl_wait_counter_eq_0)? cf_ctl_wait_counter - 1 :
    0;

  assign wait_for_cf_ctl_counter = cf_ctl_begins_xfer | ~cf_ctl_wait_counter_eq_0;
  //assign cf_ctl_irq_from_sa = cf_ctl_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cf_ctl_irq_from_sa = cf_ctl_irq;


  // synthesis attribute cf_ctl_arbitrator auto_dissolve FALSE

endmodule


module cf_ide_arbitrator (
                           // inputs:
                            cf_ide_irq,
                            cf_ide_readdata,
                            clk,
                            cpu_data_master_address_to_slave,