📄 standard.bdf

📁 这个是基于NIOS II的FPGA平台的一个CF卡的接口模块
💻 BDF
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.
*/
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(pin
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	(rect 176 336 344 352)
	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
	(text "pld_clear_n" (rect 9 0 64 12)(font "Arial" ))
	(pt 168 8)
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		(line (pt 117 12)(pt 121 8)(line_width 1))
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	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
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	(rect 176 360 344 376)
	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
	(text "in_port_to_the_button_pio[3..0]" (rect 9 0 161 12)(font "Arial" ))
	(pt 168 8)
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	(rect 368 1144 536 1160)
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	(pt 168 8)
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	(rect 176 -56 344 -40)
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)
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	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
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)
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	(annotation_block (location)(rect 264 568 360 600))
)
(pin
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	(text "cf_detect" (rect 5 0 52 12)(font "Arial" ))
	(pt 168 8)
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	(annotation_block (location)(rect 264 552 360 584))
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	(pt 168 8)
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	(annotation_block (location)(rect 264 584 360 616))
)
(pin
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	(rect 664 -56 840 -40)
	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
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	(pt 0 8)
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		(line (pt 52 4)(pt 78 4)(line_width 1))
		(line (pt 52 12)(pt 78 12)(line_width 1))
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	(rect 1704 672 1880 688)
	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
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	(pt 0 8)
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(pin
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	(rect 1704 728 1880 744)
	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
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(pin
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	(pt 0 8)
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		(line (pt 52 12)(pt 52 4)(line_width 1))
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)
(pin
	(output)
	(rect 1704 944 1880 960)
	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
	(text "out_port_from_the_seven_seg_pio[1]" (rect 90 0 274 12)(font "Arial" ))
	(pt 0 8)
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		(line (pt 82 8)(pt 78 12)(line_width 1))
		(line (pt 78 12)(pt 82 8)(line_width 1))
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(pin
	(output)
	(rect 1704 960 1880 976)
	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
	(text "out_port_from_the_seven_seg_pio[2]" (rect 90 0 274 12)(font "Arial" ))
	(pt 0 8)
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	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
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	(pt 0 8)
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(pin
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		(line (pt 52 4)(pt 78 4)(line_width 1))
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		(line (pt 52 12)(pt 52 4)(line_width 1))
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		(line (pt 82 8)(pt 78 12)(line_width 1))
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)
(pin
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	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
	(text "out_port_from_the_seven_seg_pio[6]" (rect 90 0 274 12)(font "Arial" ))
	(pt 0 8)
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		(line (pt 52 4)(pt 78 4)(line_width 1))
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		(line (pt 78 12)(pt 82 8)(line_width 1))
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(pin
	(output)
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	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
	(text "out_port_from_the_seven_seg_pio[7]" (rect 90 0 274 12)(font "Arial" ))
	(pt 0 8)
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		(line (pt 82 8)(pt 78 12)(line_width 1))
		(line (pt 78 12)(pt 82 8)(line_width 1))
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)
(pin
	(output)
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	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
	(text "out_port_from_the_seven_seg_pio[8]" (rect 90 0 274 12)(font "Arial" ))
	(pt 0 8)
	(drawing
		(line (pt 0 8)(pt 52 8)(line_width 1))
		(line (pt 52 4)(pt 78 4)(line_width 1))
		(line (pt 52 12)(pt 78 12)(line_width 1))
		(line (pt 52 12)(pt 52 4)(line_width 1))
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		(line (pt 78 12)(pt 82 8)(line_width 1))
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)
(pin
12 3 4 5 下一页
💿 文件大小 391 K
👤 上传用户 tiger452
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#NIOS #FPGA #接口模块
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