ddr_sdram_extraction_log2.txt

这个是基于NIOS II的FPGA平台的一个CF卡的接口模块

enable node is:(reg) std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dq_enable[0]
 - asynch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dq_enable_reset[0] IC(0.213 ns) + CELL(0.425 ns)
 - synch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dq_enable[0]~feeder IC(0.000 ns) + CELL(0.040 ns)
 - clock to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|wire_dqs_clkctrl_outclk[0] IC(0.655 ns) + CELL(0.307 ns)
 - fanout to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|wire_dqs_clkctrl_outclk[0] comb IC(0.628 ns) + CELL(0.000 ns)
 \ located at LCFF_X4_Y9_N1
enable node is:(reg) std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable[0]
 - asynch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable_reset[0] IC(0.213 ns) + CELL(0.425 ns)
 - synch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable[0]~feeder IC(0.000 ns) + CELL(0.040 ns)
 - clock to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|wire_dqs_clkctrl_outclk[0] IC(0.676 ns) + CELL(0.307 ns)
 - fanout to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|wire_dqs_clkctrl_outclk[0] comb IC(0.466 ns) + CELL(0.000 ns)
 \ located at LCFF_X4_Y15_N3
enable node is:(reg) std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable[0]
 - asynch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable_reset[0] IC(0.213 ns) + CELL(0.425 ns)
 - synch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable[0]~feeder IC(0.000 ns) + CELL(0.040 ns)
 - clock to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|wire_dqs_clkctrl_outclk[0] IC(0.676 ns) + CELL(0.307 ns)
 - fanout to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|wire_dqs_clkctrl_outclk[0] comb IC(0.466 ns) + CELL(0.000 ns)
 \ located at LCFF_X4_Y15_N3
enable node is:(reg) std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dq_enable[0]
 - asynch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dq_enable_reset[0] IC(0.213 ns) + CELL(0.425 ns)
 - synch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dq_enable[0]~feeder IC(0.000 ns) + CELL(0.040 ns)
 - clock to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|wire_dqs_clkctrl_outclk[0] IC(0.655 ns) + CELL(0.307 ns)
 - fanout to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|wire_dqs_clkctrl_outclk[0] comb IC(0.628 ns) + CELL(0.000 ns)
 \ located at LCFF_X4_Y9_N1
enable node is:(reg) std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dq_enable[0]
 - asynch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dq_enable_reset[0] IC(0.213 ns) + CELL(0.425 ns)
 - synch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dq_enable[0]~feeder IC(0.000 ns) + CELL(0.040 ns)
 - clock to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|wire_dqs_clkctrl_outclk[0] IC(0.655 ns) + CELL(0.307 ns)
 - fanout to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|wire_dqs_clkctrl_outclk[0] comb IC(0.628 ns) + CELL(0.000 ns)
 \ located at LCFF_X4_Y9_N1
enable node is:(reg) std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable[0]
 - asynch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable_reset[0] IC(0.213 ns) + CELL(0.425 ns)
 - synch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable[0]~feeder IC(0.000 ns) + CELL(0.040 ns)
 - clock to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|wire_dqs_clkctrl_outclk[0] IC(0.676 ns) + CELL(0.307 ns)
 - fanout to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|wire_dqs_clkctrl_outclk[0] comb IC(0.466 ns) + CELL(0.000 ns)
 \ located at LCFF_X4_Y15_N3
enable node is:(reg) std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable[0]
 - asynch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable_reset[0] IC(0.213 ns) + CELL(0.425 ns)
 - synch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable[0]~feeder IC(0.000 ns) + CELL(0.040 ns)
 - clock to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|wire_dqs_clkctrl_outclk[0] IC(0.676 ns) + CELL(0.307 ns)
 - fanout to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|wire_dqs_clkctrl_outclk[0] comb IC(0.466 ns) + CELL(0.000 ns)
 \ located at LCFF_X4_Y15_N3
enable node is:(reg) std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dq_enable[0]
 - asynch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dq_enable_reset[0] IC(0.213 ns) + CELL(0.425 ns)
 - synch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dq_enable[0]~feeder IC(0.000 ns) + CELL(0.040 ns)
 - clock to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|wire_dqs_clkctrl_outclk[0] IC(0.655 ns) + CELL(0.307 ns)
 - fanout to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|wire_dqs_clkctrl_outclk[0] comb IC(0.628 ns) + CELL(0.000 ns)
 \ located at LCFF_X4_Y9_N1
enable node is:(reg) std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dq_enable[0]
 - asynch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dq_enable_reset[0] IC(0.213 ns) + CELL(0.425 ns)
 - synch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dq_enable[0]~feeder IC(0.000 ns) + CELL(0.040 ns)
 - clock to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|wire_dqs_clkctrl_outclk[0] IC(0.655 ns) + CELL(0.307 ns)
 - fanout to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|wire_dqs_clkctrl_outclk[0] comb IC(0.628 ns) + CELL(0.000 ns)
 \ located at LCFF_X4_Y9_N1
enable node is:(reg) std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable[0]
 - asynch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable_reset[0] IC(0.213 ns) + CELL(0.425 ns)
 - synch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable[0]~feeder IC(0.000 ns) + CELL(0.040 ns)
 - clock to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|wire_dqs_clkctrl_outclk[0] IC(0.676 ns) + CELL(0.307 ns)
 - fanout to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|wire_dqs_clkctrl_outclk[0] comb IC(0.466 ns) + CELL(0.000 ns)
 \ located at LCFF_X4_Y15_N3
enable node is:(reg) std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable[0]
 - asynch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable_reset[0] IC(0.213 ns) + CELL(0.425 ns)
 - synch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable[0]~feeder IC(0.000 ns) + CELL(0.040 ns)
 - clock to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|wire_dqs_clkctrl_outclk[0] IC(0.676 ns) + CELL(0.307 ns)
 - fanout to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|wire_dqs_clkctrl_outclk[0] comb IC(0.466 ns) + CELL(0.000 ns)
 \ located at LCFF_X4_Y15_N3
enable node is:(reg) std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable[0]
 - asynch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable_reset[0] IC(0.213 ns) + CELL(0.425 ns)
 - synch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable[0]~feeder IC(0.000 ns) + CELL(0.040 ns)
 - clock to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|wire_dqs_clkctrl_outclk[0] IC(0.676 ns) + CELL(0.307 ns)
 - fanout to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|wire_dqs_clkctrl_outclk[0] comb IC(0.466 ns) + CELL(0.000 ns)
 \ located at LCFF_X4_Y15_N3
enable node is:(reg) std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable[0]
 - asynch to std_2C35:inst|ddr