ddr_sdram_extraction_log2.txt

这个是基于NIOS II的FPGA平台的一个CF卡的接口模块

    Warning: Pin "data_to_and_from_the_ext_ssram[24]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[23]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[22]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "data_to_and_from_the_ext_ssram[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[31]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[30]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[29]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[28]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[27]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[26]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[25]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[24]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[23]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[22]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Warning: Pin "ext_flash_enet_bus_data[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: Timing Analysis found one or more latches implemented as combinational loops
    Warning: Node "std_2C35:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_updatedr~8" is a latch
    Warning: Node "std_2C35:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_updateir~7" is a latch
Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
Info: Found combinational loop of 1 nodes
    Info: Node "std_2C35:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_updatedr~8"
Info: Found combinational loop of 1 nodes
    Info: Node "std_2C35:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_updateir~7"
enable node is:(reg) std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable[0]
 - asynch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable_reset[0] IC(0.213 ns) + CELL(0.425 ns)
 - synch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable[0]~feeder IC(0.000 ns) + CELL(0.040 ns)
 - clock to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|wire_dqs_clkctrl_outclk[0] IC(0.676 ns) + CELL(0.307 ns)
 - fanout to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|wire_dqs_clkctrl_outclk[0] comb IC(0.466 ns) + CELL(0.000 ns)
 \ located at LCFF_X4_Y15_N3
enable node is:(reg) std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable[0]
 - asynch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable_reset[0] IC(0.213 ns) + CELL(0.425 ns)
 - synch to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable[0]~feeder IC(0.000 ns) + CELL(0.040 ns)
 - clock to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|wire_dqs_clkctrl_outclk[0] IC(0.676 ns) + CELL(0.307 ns)
 - fanout to std_2C35:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|wire_dqs_clkctrl_outclk[0] comb IC(0.466 ns) + CELL(0.000 ns)
 \ located at LCFF_X4_Y15_N3