ddr_sdram_example_driver.v

这个是基于NIOS II的FPGA平台的一个CF卡的接口模块

            begin
              if (wdata_req)
                  writes_remaining <= writes_remaining + (size - 1);
              else 
                writes_remaining <= writes_remaining + size;
            end
          else if ((wdata_req) && (writes_remaining > 0))
              //size
              writes_remaining <= writes_remaining - 1'b1;

          else 
            writes_remaining <= writes_remaining;
          if (read_req && local_ready)
            begin
              if (local_rdata_valid)
                  reads_remaining <= reads_remaining + (size - 1);
              else 
                reads_remaining <= reads_remaining + size;
            end
          else if ((local_rdata_valid) && (reads_remaining > 0))
              reads_remaining <= reads_remaining - 1'b1;
          else 
            reads_remaining <= reads_remaining;
          case (state)
          
              4'd0: begin
                  reached_max_count <= 0;
                  if (avalon_burst_mode == 0)
                    begin
                      if (1 == 0)
                          state <= 5;
                      else 
                        state <= 1;
                    end
                  else 
                    begin
                      burst_begin <= 1;
                      write_req <= 1'b1;
                      state <= 10;
                    end
                  dgen_enable <= 1'b1;
                  //Reset just in case!
                  writes_remaining <= 0;
          
                  reads_remaining <= 0;
              end // 4'd0 
          
              4'd1: begin
                  write_req <= 1'b1;
                  dgen_enable <= 1'b1;
                  if (local_ready && write_req)
                      if (reached_max_count)
                        begin
                          state <= 2;
                          write_req <= 1'b0;
                          reset_address <= 1'b1;
                        end
              end // 4'd1 
          
              4'd10: begin
                  reset_address <= 1'b0;
                  write_req <= 1'b1;
                  burst_begin <= 0;
                  if (local_ready)
                    begin
                      burst_beat_count <= burst_beat_count + 1;
                      state <= 12;
                    end
              end // 4'd10 
          
              4'd11: begin
                  reset_address <= 1'b0;
                  read_req <= 1'b1;
                  if (! local_ready)
                    begin
                      burst_begin <= 0;
                      state <= 13;
                    end
                  if (avalon_read_burst_max_address)
                    begin
                      read_req <= 1'b0;
                      reset_address <= 1'b1;
                      test_complete <= 1'b1;
                      burst_beat_count <= 0;
                      state <= 4;
                    end
              end // 4'd11 
          
              4'd12: begin
                  write_req <= 1'b1;
                  if (local_ready)
                      if (burst_beat_count == size - 1)
                        begin
                          if (reached_max_count)
                            begin
                              write_req <= 1'b0;
                              burst_beat_count <= 0;
                              reset_address <= 1'b1;
                              dgen_enable <= 1'b0;
                              state <= 2;
                            end
                          else 
                            begin
                              burst_begin <= 1;
                              write_req <= 1'b1;
                              burst_beat_count <= 0;
                              state <= 10;
                            end
                        end
                      else 
                        burst_beat_count <= burst_beat_count + 1;
              end // 4'd12 
          
              4'd13: begin
                  read_req <= 1'b1;
                  if (local_ready)
                    begin
                      burst_begin <= 1;
                      read_req <= 1'b1;
                      state <= 11;
                    end
                  else if (avalon_read_burst_max_address)
                    begin
                      read_req <= 1'b0;
                      reset_address <= 1'b1;
                      test_complete <= 1'b1;
                      dgen_enable <= 1'b0;
                      state <= 4;
                    end
              end // 4'd13 
          
              4'd2: begin
                  if (avalon_burst_mode == 0)
                    begin
                      if (writes_remaining == 0)
                        begin
                          state <= 3;
                          dgen_enable <= 1'b0;
                        end
                    end
                  else 
                    begin
                      dgen_enable <= 1'b1;
                      burst_begin <= 1;
                      read_req <= 1'b1;
                      reset_address <= 1'b0;
                      state <= 11;
                    end
              end // 4'd2 
          
              4'd3: begin
                  read_req <= 1'b1;
                  dgen_enable <= 1'b1;
                  if (local_ready && read_req)
                      if (reached_max_count)
                        begin
                          state <= 4;
                          read_req <= 1'b0;
                          reset_address <= 1'b1;
                        end
              end // 4'd3 
          
              4'd4: begin
                  if (avalon_burst_mode == 0)
                    begin
                      if (reads_remaining == 0)
                        begin
                          state <= 0;
                          dgen_enable <= 1'b0;
                          test_complete <= 1'b1;
                        end
                    end
                  else 
                    begin
                      if (reads_remaining == 1)
                          dgen_enable <= 1'b0;
                      if (reads_remaining == 0)
                        begin
                          dgen_enable <= 1'b1;
                          burst_begin <= 1;
                          write_req <= 1'b1;
                          read_req <= 1'b0;
                          reset_address <= 1'b0;
                          burst_beat_count <= 0;
                          state <= 10;
                        end
                    end
              end // 4'd4 
          
              4'd5: begin
                  write_req <= 1'b1;
                  dgen_enable <= 1'b1;
                  wait_first_write_data <= 1'b1;
                  if (local_ready)
                    begin
                      state <= 6;
                      write_req <= 1'b0;
                    end
              end // 4'd5 
          
              4'd6: begin
                  if (writes_remaining == 0)
                    begin
                      state <= 7;
                      dgen_load <= 1'b1;
                    end
              end // 4'd6 
          
              4'd7: begin
                  read_req <= 1'b1;
                  dgen_enable <= 1'b1;
                  if (local_ready)
                    begin
                      state <= 8;
                      read_req <= 1'b0;
                    end
              end // 4'd7 
          
              4'd8: begin
                  if (reads_remaining == 0)
                      if (1)
                        begin
                          reset_address <= 1'b1;
                          dgen_enable <= 1'b0;
                          state <= 0;
                          test_complete <= 1'b1;
                        end
                      else 
                        state <= 5;
              end // 4'd8 
          
          endcase // state
          if (reset_address)
            begin
              //(others => '0')
              cs_addr <= MIN_CHIPSEL;

              row_addr <= 0;
              bank_addr <= 0;
              col_addr <= 0;
            end
          else if ((((local_ready && write_req) && (state == 1))) || ((local_ready && read_req) && (state == 3)) || ((local_ready) && ((state == 7) || (state == 10) || (state == 11) || (state == 13))))
              if (col_addr >= MAX_COL)
                begin
                  col_addr <= 0;
                  if (row_addr == MAX_ROW)
                    begin
                      row_addr <= 0;
                      if (bank_addr == MAX_BANK)
                        begin
                          bank_addr <= 0;
                          if (cs_addr == MAX_CHIPSEL)
                              //reached_max_count <= TRUE
                              //(others => '0')
                              cs_addr <= MIN_CHIPSEL;

                          else 
                            cs_addr <= cs_addr + 1'b1;
                        end
                      else 
                        bank_addr <= bank_addr + 1'b1;
                    end
                  else 
                    row_addr <= row_addr + 1'b1;
                end
              else 
                col_addr <= col_addr + (1 * 2);
        end
    end


  //------------------------------------------------------------
  //LFSR re-load data storage
  //Comparator masking and test pass signal generation
  //------------------------------------------------------------
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
        begin
          dgen_ldata <= 0;
          last_wdata_req <= 1'b0;
          //all ones
          compare_valid <= -1;

          //all ones
          compare_valid_reg <= -1;

          pnf_persist <= 1'b1;
          pnf_persist1 <= 1'b1;
          //all ones
          compare_reg <= -1;

          last_rdata_valid <= 1'b0;
        end
      else 
        begin
          last_wdata_req <= wdata_req;
          last_rdata_valid <= local_rdata_valid;
          compare_reg <= compare;
          if (wdata_req)
              //Store the data from the first write in a burst 
              //Used to reload the lfsr for the first read in a burst in WRITE 1, READ 1 mode

              if (wait_first_write_data)
                  dgen_ldata <= dgen_data;
          //Enable the comparator result when read data is valid
          if (last_rdata_valid)
              compare_valid <= compare_reg;
          //Create the overall persistent passnotfail output
          if (~&compare_valid)
              pnf_persist1 <= 1'b0;
          //Extra register stage to help Tco / Fmax on comparator output pins
          compare_valid_reg <= compare_valid;

          pnf_persist <= pnf_persist1;
        end
    end




endmodule