readme.txt

这个是基于NIOS II的FPGA平台的一个CF卡的接口模块

readme - Standard Design



Overview:

This design is provided for all Nios development boards and highlights many of the standard features of the Nios II processor.

Contents of the System:

 - Nios II/s Core
 - JTAG Debug Module (Level 1)
 - DDR SDRAM Controller (32MB)
 - SSRAM Controller (2MB)
 - CFI Flash Memory Interface (16MB)
 - EPCS Controller (with bootloader)
 - JTAG UART
 - UART (RS-232)
 - Two Timers
 - Ethernet Interface
 - LED PIO
 - Seven Segment Display PIO
 - Push Button PIO
 - LCD Display Interface
 - System ID Peripheral



Hardware Specs:

 - Fmax > 85MHz
 - Resource Usage < 4500 LEs
 - Onchip Memory Usage < 7KB
 - Two PLLs 
 - Up to four 9-bit DSP elements



Supported Software Examples:

 - Blank Project
 - Hello World
 - Board Diagnostic
 - Count Binary
 - Dhrystone
 - Hello Free-Standing
 - Hello LED
 - Hello MicroC/OS II
 - Hello World Small
 - MicroC/OS-II Message Box
 - Memory Test
 - MicroC/OS-II Tutorial
 - Simple Sockets Server
 - Web Server
 - Zip File System



Further Notes:

 - Due to the library paths that are coded into the Quartus settings for this project, if a user wishes to modify the hardware
   design they must first strip out any old paths from within the project settings file (qsf).  An example of this is as below:

set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:auto_verify_ddr_timing.tcl"
set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_tb_functions.vhd"
set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_functions.vhd"
set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_input_buf.vhd"
set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_timers.vhd"
set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_avalon_if.vhd"
set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_bank_details.vhd"
set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_controller.vhd"
set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_init.vhd"
set_global_assignment -name VERILOG_FILE "C:/niosII_cycloneII_2c35/full_featured/ddr_sdram_auk_ddr_dqs_group.v"
set_global_assignment -name VERILOG_FILE "C:/niosII_cycloneII_2c35/full_featured/ddr_sdram_auk_ddr_clk_gen.v"
set_global_assignment -name VERILOG_FILE "C:/niosII_cycloneII_2c35/full_featured/ddr_sdram_auk_ddr_datapath.v"
set_global_assignment -name VERILOG_FILE "C:/niosII_cycloneII_2c35/full_featured/ddr_sdram_auk_ddr_sdram.v"
set_global_assignment -name VERILOG_FILE "C:/niosII_cycloneII_2c35/full_featured/ddr_sdram.v"
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:auto_add_ddr_constraints.tcl"

   Once these have been removed regenerate the embedded system in SOPC Builder to recreate new paths for the DDR on the local machine.

 - DDR memory is the main memory of the system, however SSRAM has a faster access speed (when using the same clock frequencies).