ddr_sdram.v

这个是基于NIOS II的FPGA平台的一个CF卡的接口模块

// GENERATION: XML

// ============================================================
// Megafunction Name(s):
// 			ddr_sdram_auk_ddr_sdram
// ============================================================
// Generated by DDR SDRAM Controller 3.2.0 [Altera, IP Toolbench v1.2.9 build43]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2005 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera.  Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner.  Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors.  No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.


module ddr_sdram (
	clk,
	write_clk,
	reset_n,
	local_read_req,
	local_write_req,
	local_addr,
	local_wdata,
	local_be,
	local_ready,
	local_rdata,
	local_rdata_valid,
	clk_to_sdram,
	clk_to_sdram_n,
	ddr_cs_n,
	ddr_cke,
	ddr_a,
	ddr_ba,
	ddr_ras_n,
	ddr_cas_n,
	ddr_we_n,
	ddr_dm,
	ddr_dq,
	ddr_dqs);


	input		clk;
	input		write_clk;
	input		reset_n;
	input		local_read_req;
	input		local_write_req;
	input	[22:0]	local_addr;
	input	[31:0]	local_wdata;
	input	[3:0]	local_be;
	output		local_ready;
	output	[31:0]	local_rdata;
	output		local_rdata_valid;
	output		clk_to_sdram;
	output		clk_to_sdram_n;
	output		ddr_cs_n;
	output		ddr_cke;
	output	[12:0]	ddr_a;
	output	[1:0]	ddr_ba;
	output		ddr_ras_n;
	output		ddr_cas_n;
	output		ddr_we_n;
	output	[1:0]	ddr_dm;
	inout	[15:0]	ddr_dq;
	inout	[1:0]	ddr_dqs;

	wire signal_wire0 = 1'b0;
	wire [0:0] signal_wire1 = 1'b1;
	wire signal_wire2 = 1'b0;
	wire signal_wire3 = 1'b0;
	wire signal_wire4 = 1'b0;
	wire [2:0] signal_wire5 = 3'b110;
	wire [2:0] signal_wire6 = 3'b001;
	wire signal_wire7 = 1'b0;
	wire signal_wire8 = 1'b0;
	wire signal_wire9 = 1'b0;
	wire [2:0] signal_wire10 = 3'b010;
	wire [3:0] signal_wire11 = 4'b0100;
	wire [1:0] signal_wire12 = 2'b01;
	wire [2:0] signal_wire13 = 3'b010;
	wire [2:0] signal_wire14 = 3'b010;
	wire [4:0] signal_wire15 = 5'b00111;
	wire [1:0] signal_wire16 = 2'b10;
	wire [15:0] signal_wire17 = 16'b0000001010010111;
	wire [15:0] signal_wire18 = 16'b0100001001101000;

	ddr_sdram_auk_ddr_sdram	ddr_sdram_auk_ddr_sdram_inst(
		.resynch_clk(clk),
		.postamble_clk(write_clk),
		.clk(clk),
		.reset_n(reset_n),
		.write_clk(write_clk),
		.capture_clk(signal_wire0),
		.local_read_req(local_read_req),
		.local_write_req(local_write_req),
		.local_addr(local_addr),
		.local_wdata(local_wdata),
		.local_be(local_be),
		.local_size(signal_wire1),
		.local_burstbegin(signal_wire2),
		.local_refresh_req(signal_wire3),
		.local_autopch_req(signal_wire4),
		.mem_tcl(signal_wire5),
		.mem_bl(signal_wire6),
		.mem_btype(signal_wire7),
		.mem_dll_en(signal_wire8),
		.mem_drv_str(signal_wire9),
		.mem_trcd(signal_wire10),
		.mem_tras(signal_wire11),
		.mem_twtr(signal_wire12),
		.mem_twr(signal_wire13),
		.mem_trp(signal_wire14),
		.mem_trfc(signal_wire15),
		.mem_tmrd(signal_wire16),
		.mem_trefi(signal_wire17),
		.mem_tinit_time(signal_wire18),
		.local_ready(local_ready),
		.local_rdata(local_rdata),
		.local_rdata_valid(local_rdata_valid),
		.clk_to_sdram(clk_to_sdram),
		.clk_to_sdram_n(clk_to_sdram_n),
		.ddr_cs_n(ddr_cs_n),
		.ddr_cke(ddr_cke),
		.ddr_a(ddr_a),
		.ddr_ba(ddr_ba),
		.ddr_ras_n(ddr_ras_n),
		.ddr_cas_n(ddr_cas_n),
		.ddr_we_n(ddr_we_n),
		.ddr_dm(ddr_dm),
		.ddr_dq(ddr_dq),
		.ddr_dqs(ddr_dqs));

	defparam
		ddr_sdram_auk_ddr_sdram_inst.gMEM_TYPE = "ddr_sdram",
		ddr_sdram_auk_ddr_sdram_inst.gLOCAL_DATA_BITS = 32,
		ddr_sdram_auk_ddr_sdram_inst.gLOCAL_BURST_LEN = 1,
		ddr_sdram_auk_ddr_sdram_inst.gLOCAL_BURST_LEN_BITS = 1,
		ddr_sdram_auk_ddr_sdram_inst.gLOCAL_AVALON_IF = "true",
		ddr_sdram_auk_ddr_sdram_inst.gMEM_CHIPSELS = 1,
		ddr_sdram_auk_ddr_sdram_inst.gMEM_CHIP_BITS = 0,
		ddr_sdram_auk_ddr_sdram_inst.gMEM_ROW_BITS = 13,
		ddr_sdram_auk_ddr_sdram_inst.gMEM_BANK_BITS = 2,
		ddr_sdram_auk_ddr_sdram_inst.gMEM_COL_BITS = 9,
		ddr_sdram_auk_ddr_sdram_inst.gMEM_DQ_PER_DQS = 8,
		ddr_sdram_auk_ddr_sdram_inst.gMEM_PCH_BIT = 10,
		ddr_sdram_auk_ddr_sdram_inst.gREG_DIMM = "false",
		ddr_sdram_auk_ddr_sdram_inst.gPIPELINE_COMMANDS = "true",
		ddr_sdram_auk_ddr_sdram_inst.gEXTRA_PIPELINE_REGS = "false",
		ddr_sdram_auk_ddr_sdram_inst.gFAMILY = "Cyclone II",
		ddr_sdram_auk_ddr_sdram_inst.gPIPELINE_READDATA = "true",
		ddr_sdram_auk_ddr_sdram_inst.gUSER_REFRESH = "false",
		ddr_sdram_auk_ddr_sdram_inst.gADDR_CMD_NEGEDGE = "true",
		ddr_sdram_auk_ddr_sdram_inst.gRESYNCH_CYCLE = 1,
		ddr_sdram_auk_ddr_sdram_inst.gINTER_RESYNCH = "false",
		ddr_sdram_auk_ddr_sdram_inst.gPOSTAMBLE_CYCLE = 1,
		ddr_sdram_auk_ddr_sdram_inst.gINTER_POSTAMBLE = "false",
		ddr_sdram_auk_ddr_sdram_inst.gDLL_INPUT_FREQUENCY = "11764ps";
endmodule