verify_timing_for_ddr_sdram.tcl

这个是基于NIOS II的FPGA平台的一个CF卡的接口模块

##
##
##  Run this TCL script after successfully compiling
##  your DDR/DDR2-SDRAM v3.2.0 Project in QUARTUS-II
##
##  THIS MAY TAKE SOME TIME!
##
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set actual_pwd [file normalize [pwd]]
set correct_pwd [file normalize [file dirname [info script]]]
if { $actual_pwd != $correct_pwd } {

post_message -type warning "[info script] is not being run from the directory it resides in. Should be run from $correct_pwd not $actual_pwd"
post_message -type warning "Changing to $correct_pwd in order to continue."
cd $correct_pwd
}


source ddr_lib_path.tcl
package require ::ddr::settings



global variation_name
if { [regexp {^verify_timing_for_([\w\d\-_]+).tcl$} [file tail [info script]]  x variation_name] != 1} {
error "Couldn't extract variation name from [file tail [info script]]"
}

puts "Detected variation name: $variation_name"


::ddr::settings::read "${variation_name}_ddr_settings.txt" settings_array
puts "Running verify_ddr_timing_main.tcl from $settings_array(current_script_working_dir)"


source [file join $settings_array(current_script_working_dir) verify_ddr_timing_main.tcl]