ddr_sdram_bb.v

这个是基于NIOS II的FPGA平台的一个CF卡的接口模块

// Generated by DDR SDRAM Controller 3.2.0 [Altera, IP Toolbench v1.2.9 build43]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2005 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera.  Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner.  Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors.  No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.

module ddr_sdram (
	clk,
	write_clk,
	reset_n,
	local_read_req,
	local_write_req,
	local_addr,
	local_wdata,
	local_be,
	local_ready,
	local_rdata,
	local_rdata_valid,
	clk_to_sdram,
	clk_to_sdram_n,
	ddr_cs_n,
	ddr_cke,
	ddr_a,
	ddr_ba,
	ddr_ras_n,
	ddr_cas_n,
	ddr_we_n,
	ddr_dm,
	ddr_dq,
	ddr_dqs);

	input		clk;
	input		write_clk;
	input		reset_n;
	input		local_read_req;
	input		local_write_req;
	input	[22:0]	local_addr;
	input	[31:0]	local_wdata;
	input	[3:0]	local_be;
	output		local_ready;
	output	[31:0]	local_rdata;
	output		local_rdata_valid;
	output		clk_to_sdram;
	output		clk_to_sdram_n;
	output		ddr_cs_n;
	output		ddr_cke;
	output	[12:0]	ddr_a;
	output	[1:0]	ddr_ba;
	output		ddr_ras_n;
	output		ddr_cas_n;
	output		ddr_we_n;
	output	[1:0]	ddr_dm;
	inout	[15:0]	ddr_dq;
	inout	[1:0]	ddr_dqs;
endmodule