alu.vhd

4bit ALU 利用vhdl语言编写的4位ALU 开发环境是在windows下

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity alu is
port( a,b: in std_logic_vector(3 downto 0);
      s: in std_logic_vector(3 downto 0);
      cin: in std_logic;
      f: out std_logic_vector(3 downto 0);
      cout: out std_logic
);
end entity alu;

architecture action of alu is   
  constant add : std_logic_vector(3 downto 0) := "0000";
  constant sub : std_logic_vector(3 downto 0) := "0001";
  constant shift_l : std_logic_vector(3 downto 0) := "0010";
  constant shift_r : std_logic_vector(3 downto 0) := "0011";
  constant and_f : std_logic_vector(3 downto 0) := "0100";
  constant or_f : std_logic_vector(3 downto 0) := "0101";
  constant not_f : std_logic_vector(3 downto 0) := "0110";
  constant t_c : std_logic_vector(3 downto 0) := "0111";
  constant inv : std_logic_vector(3 downto 0) := "1000";
begin 
process(a, b, cin, s)
  variable aa_1, aa, bb, ff: std_logic_vector(4 downto 0);
  variable cc: std_logic;
  begin
    aa := '0' & a;
    bb := '0' & b;
    aa_1 := '1' & a;
    case s is
      when add => ff := aa+bb+cin; cc := ff(4); 
      when sub => ff := aa_1-bb-cin; cc := not ff(4); 
      when shift_l =>ff(3 downto 0) := a(2 downto 0) & a(3);cc := '0'; 
      when shift_r => ff(3 downto 0) := a(0) & a(3 downto 1);cc := '0';
      when and_f => ff(3 downto 0) := a and b; cc := '0'; 
      when or_f => ff(3 downto 0) := a or b; cc := '0'; 
      when not_f => ff(3 downto 0) := not a; cc := '0'; 
      when t_c => if(cin='1') then ff(3 downto 0) := not a + '1'; cc := '0';else ff(3 downto 0) := a; end if;
      when inv => if a(3)='1' then ff(3 downto 0) := a(3) & not a(2 downto 0) + "0001"; cc := cin;
                  else ff(3 downto 0) := a; cc := cin; end if; 
      when others => null;
    end case;
f <= ff(3 downto 0);
cout <= cc;
end process;

end architecture action;