q7230.map.rpt

来自「PLD-N分频程序」· RPT 代码 · 共 243 行 · 第 1/2 页

      |-- altshift:result_ext_latency_ffs


+---------------------------------------------------+
; User-Specified and Inferred Latches               ;
+-----------------------------------------------+---+
; Latch Name                                    ;   ;
+-----------------------------------------------+---+
; Q[0]                                          ;   ;
; Q[1]                                          ;   ;
; Q[2]                                          ;   ;
; Q[3]                                          ;   ;
; Q[4]                                          ;   ;
; Q[5]                                          ;   ;
; Q[6]                                          ;   ;
; Q[7]                                          ;   ;
; Number of user-specified and inferred latches ; 8 ;
+-----------------------------------------------+---+


+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                  ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |TOP                       ; 28         ; 19   ; |TOP                ;
+----------------------------+------------+------+---------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/PLD-Test/NEW/Q7230/Q7230.map.eqn.


+---------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                          ;
+----------------------------------+-----------------+----------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path                                               ;
+----------------------------------+-----------------+----------------------------------------------------------------------------+
; TOP.vhd                          ; yes             ; D:/PLD-Test/NEW/Q7230/TOP.vhd                                              ;
; lpm_add_sub.tdf                  ; yes             ; d:/comsof/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf         ;
; addcore.inc                      ; yes             ; d:/comsof/altera/quartus42/libraries/megafunctions/addcore.inc             ;
; look_add.inc                     ; yes             ; d:/comsof/altera/quartus42/libraries/megafunctions/look_add.inc            ;
; bypassff.inc                     ; yes             ; d:/comsof/altera/quartus42/libraries/megafunctions/bypassff.inc            ;
; altshift.inc                     ; yes             ; d:/comsof/altera/quartus42/libraries/megafunctions/altshift.inc            ;
; alt_stratix_add_sub.inc          ; yes             ; d:/comsof/altera/quartus42/libraries/megafunctions/alt_stratix_add_sub.inc ;
; alt_mercury_add_sub.inc          ; yes             ; d:/comsof/altera/quartus42/libraries/megafunctions/alt_mercury_add_sub.inc ;
; aglobal42.inc                    ; yes             ; d:/comsof/altera/quartus42/libraries/megafunctions/aglobal42.inc           ;
; addcore.tdf                      ; yes             ; d:/comsof/altera/quartus42/libraries/megafunctions/addcore.tdf             ;
; a_csnbuffer.inc                  ; yes             ; d:/comsof/altera/quartus42/libraries/megafunctions/a_csnbuffer.inc         ;
; a_csnbuffer.tdf                  ; yes             ; d:/comsof/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf         ;
; look_add.tdf                     ; yes             ; d:/comsof/altera/quartus42/libraries/megafunctions/look_add.tdf            ;
; altshift.tdf                     ; yes             ; d:/comsof/altera/quartus42/libraries/megafunctions/altshift.tdf            ;
+----------------------------------+-----------------+----------------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 28                   ;
; Total registers      ; 10                   ;
; I/O pins             ; 19                   ;
; Shareable expanders  ; 16                   ;
; Parallel expanders   ; 6                    ;
; Maximum fan-out node ; count[0]             ;
; Maximum fan-out      ; 19                   ;
; Total fan-out        ; 268                  ;
; Average fan-out      ; 4.25                 ;
+----------------------+----------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 156 11/29/2004 SJ Web Edition
    Info: Processing started: Wed Jan 04 09:38:15 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Q7230 -c Q7230
Info: Found 2 design units, including 1 entities, in source file TOP.vhd
    Info: Found design unit 1: TOP-a
    Info: Found entity 1: TOP
Warning: VHDL Signal Declaration warning at TOP.vhd(20): ignored default value for signal "count"
Warning: VHDL Signal Declaration warning at TOP.vhd(21): ignored default value for signal "Q"
Warning: VHDL Signal Declaration warning at TOP.vhd(22): ignored default value for signal "CP_Q"
Warning: VHDL Signal Declaration warning at TOP.vhd(23): ignored default value for signal "D_Q"
Warning: VHDL Process Statement warning at TOP.vhd(48): signal "NAB" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at TOP.vhd(48): signal "CP_Q" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at TOP.vhd(58): signal "Din" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at TOP.vhd(53): signal or variable "Q" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "Q" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at TOP.vhd(69): signal "D_Q" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Found 1 design units, including 1 entities, in source file ../../../comsof/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file ../../../comsof/altera/quartus42/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file ../../../comsof/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file ../../../comsof/altera/quartus42/libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file ../../../comsof/altera/quartus42/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Ignored 8 buffer(s)
    Info: Ignored 8 SOFT buffer(s)
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "CLK" to global clock signal
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "CLK" to global clock signal
Info: Implemented 63 device resources after synthesis - the final resource count might be different
    Info: Implemented 15 input pins
    Info: Implemented 4 output pins
    Info: Implemented 28 macrocells
    Info: Implemented 16 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings
    Info: Processing ended: Wed Jan 04 09:38:36 2006
    Info: Elapsed time: 00:00:22