_primary.vhd

altera i2c host/device

library verilog;
use verilog.vl_types.all;
entity m3s008br is
    port(
        clk             : in     vl_logic;
        nrst            : in     vl_logic;
        clkenab         : in     vl_logic;
        softreset       : in     vl_logic;
        sendstart       : in     vl_logic;
        iflg            : in     vl_logic;
        ready           : in     vl_logic;
        intscl          : in     vl_logic;
        clearsta        : out    vl_logic;
        startcomp       : out    vl_logic;
        assertda_s      : out    vl_logic
    );
end m3s008br;