_primary.vhd

altera i2c host/device

library verilog;
use verilog.vl_types.all;
entity m3s009br is
    port(
        clk             : in     vl_logic;
        nrst            : in     vl_logic;
        clkenab         : in     vl_logic;
        softreset       : in     vl_logic;
        sendstop        : in     vl_logic;
        intscl          : in     vl_logic;
        clearstp        : out    vl_logic;
        assertda_p      : out    vl_logic;
        releaseda       : out    vl_logic
    );
end m3s009br;