_primary.vhd

altera i2c host/device

library verilog;
use verilog.vl_types.all;
entity m3s004br is
    port(
        clk             : in     vl_logic;
        nrst            : in     vl_logic;
        clkenab         : in     vl_logic;
        iscl            : in     vl_logic;
        isda            : in     vl_logic;
        intscl          : out    vl_logic;
        intsda          : out    vl_logic;
        srclkenab       : out    vl_logic
    );
end m3s004br;