_primary.vhd

altera i2c host/device

library verilog;
use verilog.vl_types.all;
entity m3s007br is
    port(
        clk             : in     vl_logic;
        nrst            : in     vl_logic;
        clkenab         : in     vl_logic;
        maclkenab       : in     vl_logic;
        cntrlenab       : in     vl_logic;
        softreset       : in     vl_logic;
        mastmode        : in     vl_logic;
        iflg            : in     vl_logic;
        intscl          : in     vl_logic;
        busclkenab      : in     vl_logic;
        errcond         : in     vl_logic;
        gotoidle        : in     vl_logic;
        flagrs          : in     vl_logic;
        starttfer       : in     vl_logic;
        txdata          : in     vl_logic;
        enopenab2       : in     vl_logic;
        oscl            : out    vl_logic;
        step            : out    vl_logic;
        opclkdata       : out    vl_logic;
        ready           : out    vl_logic;
        openab2         : out    vl_logic
    );
end m3s007br;