complex_bibus2.xrf

设计与验证verilog hdl

vendor_name = Synplicity
source_file = 0, noname, synplify
source_file = 1, c:\eda\synplicity\fpga_81\lib\altera\altera.v, synplify
source_file = 2, c:\eda\synplicity\fpga_81\lib\altera\cycloneii.v, synplify
source_file = 3, c:\eda\synplicity\fpga_81\lib\altera\altera_mf.v, synplify
source_file = 4, c:\eda\synplicity\fpga_81\lib\altera\altera_lpm.v, synplify
source_file = 5, c:\prj\example-5-1\complex_bibus\counter.v, synplify
source_file = 6, c:\prj\example-5-1\complex_bibus\decode.v, synplify
source_file = 7, c:\prj\example-5-1\complex_bibus\complex_bibus2.v, synplify
design_name=complex_bibus
instance = port, clk, , complex_bibus, 7, 2:12:2:14
instance = port, rst, , complex_bibus, 7, 2:17:2:19
instance = port, sel1, , complex_bibus, 7, 3:12:3:15
instance = port, sel2, , complex_bibus, 7, 3:18:3:21
instance = port, sel3, , complex_bibus, 7, 3:24:3:27
instance = port, data_bus[7:0], , complex_bibus, 7, 5:12:5:19
instance = port, addr[7:0], , complex_bibus, 7, 4:12:4:15
instance = comp, un1_decode_out_2_0_4_, , complex_bibus, 7, 29:19:29:93
instance = comp, un1_decode_out_2_0_5_, , complex_bibus, 7, 29:19:29:93
instance = comp, un1_decode_out_2_0_6_, , complex_bibus, 7, 29:19:29:93
instance = comp, un1_decode_out_2_0_7_, , complex_bibus, 7, 29:19:29:93
instance = comp, un1_decode_out_2_0_0_, , complex_bibus, 7, 29:19:29:93
instance = comp, un1_decode_out_2_0_1_, , complex_bibus, 7, 29:19:29:93
instance = comp, un1_decode_out_2_0_2_, , complex_bibus, 7, 29:19:29:93
instance = comp, un1_decode_out_2_0_3_, , complex_bibus, 7, 29:19:29:93
instance = comp, un5_data_bus_x_cZ, , complex_bibus, 7, 3:12:29:92
instance = comp, addr_in_7_, , complex_bibus, 7, 4:12:4:15
instance = comp, addr_in_6_, , complex_bibus, 7, 4:12:4:15
instance = comp, addr_in_5_, , complex_bibus, 7, 4:12:4:15
instance = comp, addr_in_4_, , complex_bibus, 7, 4:12:4:15
instance = comp, addr_in_3_, , complex_bibus, 7, 4:12:4:15
instance = comp, addr_in_2_, , complex_bibus, 7, 4:12:4:15
instance = comp, addr_in_1_, , complex_bibus, 7, 4:12:4:15
instance = comp, addr_in_0_, , complex_bibus, 7, 4:12:4:15
instance = comp, sel3_in, , complex_bibus, 7, 3:24:3:27
instance = comp, sel2_in, , complex_bibus, 7, 3:18:3:21
instance = comp, sel1_in, , complex_bibus, 7, 3:12:3:15
instance = comp, rst_in, , complex_bibus, 7, 2:17:2:19
instance = comp, clk_in, , complex_bibus, 7, 2:12:2:14
instance = comp, data_bus_tri_7_, , complex_bibus, 7, 5:12:5:19
instance = comp, data_bus_tri_6_, , complex_bibus, 7, 5:12:5:19
instance = comp, data_bus_tri_5_, , complex_bibus, 7, 5:12:5:19
instance = comp, data_bus_tri_4_, , complex_bibus, 7, 5:12:5:19
instance = comp, data_bus_tri_3_, , complex_bibus, 7, 5:12:5:19
instance = comp, data_bus_tri_2_, , complex_bibus, 7, 5:12:5:19
instance = comp, data_bus_tri_1_, , complex_bibus, 7, 5:12:5:19
instance = comp, data_bus_tri_0_, , complex_bibus, 7, 5:12:5:19
instance = comp, decode_inst, , complex_bibus, 7, 15:7:15:17
instance = comp, counter_inst, , complex_bibus, 7, 22:8:22:19
design_name=counter
instance = comp, cnt_out_7__Z, , counter, 5, 16:0:16:5
instance = comp, cnt_out_6__Z, , counter, 5, 16:0:16:5
instance = comp, cnt_out_5__Z, , counter, 5, 16:0:16:5
instance = comp, cnt_out_4__Z, , counter, 5, 16:0:16:5
instance = comp, cnt_out_3__Z, , counter, 5, 16:0:16:5
instance = comp, cnt_out_2__Z, , counter, 5, 16:0:16:5
instance = comp, cnt_out_1__Z, , counter, 5, 16:0:16:5
instance = comp, cnt_out_0__Z, , counter, 5, 16:0:16:5
instance = comp, un3_cnt_out_0_, , counter, 5, 20:20:20:35
instance = comp, un3_cnt_out_1_, , counter, 5, 20:20:20:35
instance = comp, un3_cnt_out_2_, , counter, 5, 20:20:20:35
instance = comp, un3_cnt_out_3_, , counter, 5, 20:20:20:35
instance = comp, un3_cnt_out_4_, , counter, 5, 20:20:20:35
instance = comp, un3_cnt_out_5_, , counter, 5, 20:20:20:35
instance = comp, un3_cnt_out_6_, , counter, 5, 20:20:20:35
instance = comp, un3_cnt_out_7_, , counter, 5, 20:20:20:35
design_name=decode
instance = comp, data_bus_out_7__Z, , decode, 6, 11:0:11:5
instance = comp, data_bus_out_6__Z, , decode, 6, 11:0:11:5
instance = comp, data_bus_out_5__Z, , decode, 6, 11:0:11:5
instance = comp, data_bus_out_4__Z, , decode, 6, 11:0:11:5
instance = comp, data_bus_out_3__Z, , decode, 6, 11:0:11:5
instance = comp, data_bus_out_2__Z, , decode, 6, 11:0:11:5
instance = comp, data_bus_out_1__Z, , decode, 6, 11:0:11:5
instance = comp, data_bus_out_0__Z, , decode, 6, 11:0:11:5
instance = comp, data_bus_out_7_0_, , decode, 6, 15:9:15:12
instance = comp, data_bus_out_7_1_, , decode, 6, 15:9:15:12
instance = comp, data_bus_out_7_2_, , decode, 6, 15:9:15:12
instance = comp, data_bus_out_7_3_, , decode, 6, 15:9:15:12
instance = comp, data_bus_out_7_4_, , decode, 6, 15:9:15:12
instance = comp, data_bus_out_7_5_, , decode, 6, 15:9:15:12
instance = comp, data_bus_out_7_6_, , decode, 6, 15:9:15:12
instance = comp, data_bus_out_7_7_, , decode, 6, 15:9:15:12
instance = comp, data_bus_out19_a_cZ, , decode, 6, 15:9:15:12
instance = comp, data_bus_out19_cZ, , decode, 6, 15:9:15:12
instance = comp, un1_data_bus_out20_1_cZ, , decode, 6, 11:0:11:5
instance = comp, data_bus_out19_0_x_cZ, , decode, 6, 15:9:15:12
instance = comp, un1_data_bus_out20_1_a_s_cZ, , decode, 6, 11:0:11:5
instance = comp, un1_data_bus_out20_1_a_x_cZ, , decode, 6, 11:0:11:5