latch.edf

设计与验证verilog hdl

(edif latch
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2006 1 2 22 48 41)
      (author "Synplicity, Inc.")
      (program "Synplify Pro" (version "8.1.0, Build 540R"))
     )
   )
  (library VIRTEX
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell IBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell OBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell BUFGP (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
  )
  (library UNILIB
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell LD (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port G (direction INPUT)
 )
         )
       )
    )
  )
  (library work
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell latch (cellType GENERIC)
       (view verilog (viewType NETLIST)
         (interface
           (port cond_1 (direction INPUT)
 )
           (port data_in (direction INPUT)
 )
           (port data_out (direction OUTPUT))
         )
         (contents
          (instance (rename data_outZ0 "data_out") (viewRef PRIM (cellRef LD (libraryRef UNILIB)))
          )
          (instance cond_1_ibuf (viewRef PRIM (cellRef BUFGP (libraryRef VIRTEX)))
          )
          (instance data_out_obuf (viewRef PRIM (cellRef OBUF (libraryRef VIRTEX)))
          )
          (instance data_in_ibuf (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (net cond_1 (joined
           (portRef cond_1)
           (portRef I (instanceRef cond_1_ibuf))
          ))
          (net data_in (joined
           (portRef data_in)
           (portRef I (instanceRef data_in_ibuf))
          ))
          (net data_out (joined
           (portRef O (instanceRef data_out_obuf))
           (portRef data_out)
          ))
          (net cond_1_c (joined
           (portRef O (instanceRef cond_1_ibuf))
           (portRef G (instanceRef data_outZ0))
          ))
          (net data_out_c (joined
           (portRef Q (instanceRef data_outZ0))
           (portRef I (instanceRef data_out_obuf))
          ))
          (net data_in_c (joined
           (portRef O (instanceRef data_in_ibuf))
           (portRef D (instanceRef data_outZ0))
          ))
         )
       )
    )
  )
  (design latch (cellRef latch (libraryRef work))
	(property PART (string "xc3s100evq100-4") (owner "Xilinx")))
)