if_mult_decode.srs

设计与验证verilog hdl

#
#
#
# Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Mon Jan 16 09:32:56 2006
#
#
#OPTIONS:"|-fixsmult|-I|C:\\prj\\Example-4-10\\decode\\if_mult\\|-I|C:\\eda\\synplicity\\fpga_81\\lib|-v2001|-devicelib|C:\\eda\\synplicity\\fpga_81\\lib\\lucent\\ec.v|-sm|-fid2|-sharing|off|-encrypt|-ui|-pro|-ram|-ll|2000"
#CUR:"C:\\eda\\synplicity\\fpga_81\\bin\\c_ver.exe":1115125636
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\lucent\\ec.v":1110443424
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\lucent\\ec.v":1110443424
#CUR:"C:\\prj\\Example-4-10\\decode\\if_mult\\if_mult_decode.v":1137138979
#CUR:"C:\\prj\\Example-4-10\\decode\\if_mult\\if_mult_decode.v":1137138979
f "C:\eda\synplicity\fpga_81\lib\lucent\ec.v"; # file 0
af .is_verilog 1;
f "C:\prj\Example-4-10\decode\if_mult\if_mult_decode.v"; # file 1
af .is_verilog 1;
@E
@ 
ftell;
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;

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b@:@444(:U(:4:RddNPM8R_B1L4k#j1RB_#Lk4NjR8_8s]9r.R4kM_8N8sr_]jk9RMN4_8_8s]9r4;R
b@:@444g:Ug:4:RddNPM8R_B1L4k#g1RB_#Lk4NgR8_8s]9rjR8N8sr_].k9RMN4_8_8s]9r4;R
b@:@4.44:U4:.:RddNPM8R_B1L.k#U1RB_#Lk.NUR8_8s]9r4R4kM_8N8sr_]jk9RMN4_8_8s]9r.;R
b@:@4.4d:Ud:.:RddNPM8R_B1Ldk#(1RB_#LkdN(R8_8s]9rjR8N8sr_]4k9RMN4_8_8s]9r.;R
b@:@444(:U(:4:RddHRMPBR1cBR1cBL1_kj#4;R
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b@:@4.44:U4:.:RddHRMPBR1.BR1.BL1_kU#.;R
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