resource_share1.vqm

设计与验证verilog hdl

//
// Written by Synplify
// Synplify 8.1.0, Build 539R.
// Wed Mar 08 17:44:23 2006
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\c:\eda\synplicity\fpga_81\lib\altera\altera.v "
// file 2 "\c:\eda\synplicity\fpga_81\lib\altera\cyclone.v "
// file 3 "\c:\eda\synplicity\fpga_81\lib\altera\altera_mf.v "
// file 4 "\c:\eda\synplicity\fpga_81\lib\altera\altera_lpm.v "
// file 5 "\c:\prj\chapter5\example-5-6\source\resource_share1.v "

// VQM4.1+ 
module resource_share1 (
  data_in,
  square
);
input [7:0] data_in ;
output [15:0] square /* synthesis syn_tristate = 1 */;
wire [12:12] un2_square_madd_4;
wire [15:9] un2_square_madd_3;
wire [13:13] un2_square_madd_2;
wire [11:11] un2_square_madd_1;
wire [9:9] un2_square_madd_0;
wire [12:12] un7_square_madd_4;
wire [15:15] un7_square_madd_3;
wire [13:9] un7_square_madd_2;
wire [11:11] un7_square_madd_1;
wire [9:9] un7_square_madd_0;
wire [6:1] un2_square_a7_b_i_x;
wire [4:0] un2_square_a5_b_i_x;
wire [2:0] un2_square_a3_b_i_x;
wire [0:0] un2_square_a1_b_i_x;
wire [6:0] un7_square_a7_b_i_x;
wire [4:1] un7_square_a5_b_i_x;
wire [2:1] un7_square_a3_b_i_x;
wire [0:0] un7_square_a1_b_i_x;
wire [14:2] square_x;
wire [7:1] data_in_c;
wire [6:6] un2_square_a1_b_0_a2_x;
wire [7:1] data_bar;
wire [6:6] un7_square_a4_b_0_a2_x;
wire [5:4] un7_square_a2_b_0_a3_x;
wire [4:4] un7_square_a3_b_0_a3_x;
wire [5:2] un7_square_a0_b_0_a3_x;
wire [2:2] un2_square_a0_b_0_a3_x;
wire [6:6] un7_square_a2_b_0_a2_x;
wire [5:5] un7_square_a6_b_i_x;
wire [4:2] un7_square_a1_b_0_a3_x;
wire [6:6] un7_square_a1_b_0_a2_x;
wire [5:3] un2_square_a1_b_0_a3_x;
wire [5:4] un2_square_a6_b_i_x;
wire [7:7] un2_square_a5_b_0_a2_x;
wire [7:6] un2_square_a3_b_0_a2_x;
wire [7:6] un2_square_a0_b_0_a2_x;
wire [6:6] un7_square_a0_b_0_a2_x;
wire [6:6] un7_square_a3_b_0_a2_x;
wire [7:6] un2_square_a2_b_0_a2_x;
wire [5:5] un2_square_a2_b_0_a3_x;
wire [1:1] un2_square_a2_b_i_x;
wire [2:0] un2_square_a4_b_i_x;
wire [7:7] un2_square_a4_b_0_a2_x;
wire [5:4] un2_square_a3_b_0_a3_x;
wire [15:15] square_i_m2_x;
wire [5:0] data_bar_cout;
wire GND ;
wire G_93 ;
wire VCC ;
wire un2_square_madd_4_add9_cout ;
wire un2_square_madd_3_add8_cout ;
wire un2_square_madd_3_add6_cout ;
wire un2_square_madd_3_add2_cout ;
wire un2_square_madd_2_add8_cout ;
wire un2_square_madd_1_add8_cout ;
wire un2_square_madd_0_add7_cout ;
wire un7_square_madd_4_add9_cout ;
wire un7_square_madd_3_add8_cout ;
wire un7_square_madd_2_add8_cout ;
wire un7_square_madd_2_add4_cout ;
wire un7_square_madd_1_add8_cout ;
wire un7_square_madd_0_add7_cout ;
wire un2_square_madd_3_add8_start_cout ;
wire un2_square_madd_3_add4_start_cout ;
wire un2_square_madd_2_add2_start_cout ;
wire un2_square_madd_0_add1_start_cout ;
wire un7_square_madd_3_add8_start_cout ;
wire un7_square_madd_2_add6_start_cout ;
wire un7_square_madd_2_add2_start_cout ;
wire un7_square_madd_0_add1_start_cout ;
wire un2_square_madd_4_add1 ;
wire un7_square_madd_4_add1 ;
wire un2_square_madd_add0 ;
wire un7_square_madd_add0 ;
wire un2_square_madd_add3 ;
wire un7_square_madd_add3 ;
wire un2_square_madd_add1 ;
wire un7_square_madd_add1 ;
wire un2_square_madd_add11 ;
wire un7_square_madd_add11 ;
wire un2_square_madd_add10 ;
wire un7_square_madd_add10 ;
wire un2_square_madd_add9 ;
wire un7_square_madd_add9 ;
wire un2_square_madd_add8 ;
wire un7_square_madd_add8 ;
wire un2_square_madd_add7 ;
wire un7_square_madd_add7 ;
wire un2_square_madd_add6 ;
wire un7_square_madd_add6 ;
wire un2_square_madd_add5 ;
wire un7_square_madd_add5 ;
wire un2_square_madd_add4 ;
wire un7_square_madd_add4 ;
wire un2_square_madd_add2 ;
wire un7_square_madd_add2 ;
wire un2_square_madd_4_add0 ;
wire un7_square_madd_4_add0 ;
wire un2_square_madd_5_add11 ;
wire un2_square_madd_5_carry_10 ;
wire un2_square_madd_5_add10 ;
wire un2_square_madd_3_add8 ;
wire un2_square_madd_5_carry_9 ;
wire un2_square_madd_5_add9 ;
wire un2_square_madd_5_carry_8 ;
wire un2_square_madd_5_add8 ;
wire un2_square_madd_2_add8 ;
wire un2_square_madd_3_add6 ;
wire un2_square_madd_5_carry_7 ;
wire un2_square_madd_5_add7 ;
wire un2_square_madd_2_add7 ;
wire un2_square_madd_3_add5 ;
wire un2_square_madd_5_carry_6 ;
wire un2_square_madd_5_add6 ;
wire un2_square_madd_2_add6 ;
wire un2_square_madd_3_add4 ;
wire un2_square_madd_5_carry_5 ;
wire un2_square_madd_5_add5 ;
wire un2_square_madd_2_add5 ;
wire un2_square_madd_5_carry_4 ;
wire un2_square_madd_5_add4 ;
wire un2_square_madd_0_add7 ;
wire un2_square_madd_2_add4 ;
wire un2_square_madd_5_carry_3 ;
wire un2_square_madd_5_add3 ;
wire un2_square_madd_0_add6 ;
wire un2_square_madd_2_add3 ;
wire un2_square_madd_5_carry_2 ;
wire un2_square_madd_5_add2 ;
wire un2_square_madd_0_add5 ;
wire un2_square_madd_2_add2 ;
wire un2_square_madd_4_add9 ;
wire un2_square_madd_4_carry_8 ;
wire un2_square_madd_4_add8 ;
wire un2_square_madd_1_add8 ;
wire un2_square_madd_4_carry_7 ;
wire un2_square_madd_4_add7 ;
wire un2_square_madd_1_add7 ;
wire un2_square_madd_4_carry_6 ;
wire un2_square_madd_4_add6 ;
wire un2_square_madd_1_add6 ;
wire un2_square_madd_3_add2 ;
wire un2_square_madd_4_carry_5 ;
wire un2_square_madd_4_add5 ;
wire un2_square_madd_1_add5 ;
wire un2_square_madd_3_add1 ;
wire un2_square_madd_4_carry_4 ;
wire un2_square_madd_4_add4 ;
wire un2_square_madd_1_add4 ;
wire un2_square_madd_4_carry_3 ;
wire un2_square_madd_4_add3 ;
wire un2_square_madd_1_add3 ;
wire un2_square_madd_4_carry_2 ;
wire un2_square_madd_4_add2 ;
wire un2_square_madd_1_add2 ;
wire un2_square_madd_4_carry_1 ;
wire un2_square_madd_1_add1 ;
wire un2_square_madd_0_add2 ;
wire un2_square_madd_4_carry_0 ;
wire un2_square_madd_0_add1 ;
wire un2_square_madd_3_carry_5 ;
wire un2_square_madd_3_carry_4 ;
wire un2_square_madd_3_carry_1 ;
wire un2_square_madd_2_carry_7 ;
wire un2_square_madd_2_carry_6 ;
wire un2_square_madd_2_carry_5 ;
wire un2_square_madd_2_carry_4 ;
wire un2_square_madd_2_carry_3 ;
wire un2_square_madd_2_carry_2 ;
wire un2_square_madd_1_carry_7 ;
wire un2_square_madd_1_carry_6 ;
wire un2_square_madd_1_carry_5 ;
wire un2_square_madd_1_carry_4 ;
wire un2_square_madd_1_carry_3 ;
wire un2_square_madd_1_carry_2 ;
wire un2_square_madd_1_carry_1 ;
wire un2_square_madd_0_carry_6 ;
wire un2_square_madd_0_carry_5 ;
wire un2_square_madd_0_carry_4 ;
wire un2_square_madd_0_add4 ;
wire un2_square_madd_0_carry_3 ;
wire un2_square_madd_0_add3 ;
wire un2_square_madd_0_carry_2 ;
wire un2_square_madd_0_carry_1 ;
wire un7_square_madd_5_add11 ;
wire un7_square_madd_carry_10 ;
wire un7_square_madd_5_add10 ;
wire un7_square_madd_carry_9 ;
wire un7_square_madd_5_add9 ;
wire un7_square_madd_carry_8 ;
wire un7_square_madd_5_add8 ;
wire un7_square_madd_carry_7 ;
wire un7_square_madd_5_add7 ;
wire un7_square_madd_4_add9 ;
wire un7_square_madd_carry_6 ;
wire un7_square_madd_5_add6 ;
wire un7_square_madd_4_add8 ;
wire un7_square_madd_carry_5 ;
wire un7_square_madd_5_add5 ;
wire un7_square_madd_4_add7 ;
wire un7_square_madd_carry_4 ;
wire un7_square_madd_5_add4 ;
wire un7_square_madd_4_add6 ;
wire un7_square_madd_carry_3 ;
wire un7_square_madd_5_add3 ;
wire un7_square_madd_4_add5 ;
wire un7_square_madd_carry_2 ;
wire un7_square_madd_5_add2 ;
wire un7_square_madd_4_add4 ;
wire un7_square_madd_carry_1 ;
wire un7_square_madd_0_add4 ;
wire un7_square_madd_4_add3 ;
wire un7_square_madd_carry_0 ;
wire un7_square_madd_0_add3 ;
wire un7_square_madd_4_add2 ;
wire un7_square_madd_5_carry_10 ;
wire un7_square_madd_3_add8 ;
wire un7_square_madd_5_carry_9 ;
wire un7_square_madd_5_carry_8 ;
wire un7_square_madd_2_add8 ;
wire un7_square_madd_5_carry_7 ;
wire un7_square_madd_2_add7 ;
wire un7_square_madd_5_carry_6 ;
wire un7_square_madd_2_add6 ;
wire un7_square_madd_5_carry_5 ;
wire un7_square_madd_5_carry_4 ;
wire un7_square_madd_0_add7 ;
wire un7_square_madd_5_carry_3 ;
wire un7_square_madd_0_add6 ;
wire un7_square_madd_2_add3 ;
wire un7_square_madd_5_carry_2 ;
wire un7_square_madd_0_add5 ;
wire un7_square_madd_2_add2 ;
wire un7_square_madd_4_carry_8 ;
wire un7_square_madd_1_add8 ;
wire un7_square_madd_4_carry_7 ;
wire un7_square_madd_1_add7 ;
wire un7_square_madd_4_carry_6 ;
wire un7_square_madd_1_add6 ;
wire un7_square_madd_2_add4 ;
wire un7_square_madd_4_carry_5 ;
wire un7_square_madd_1_add5 ;
wire un7_square_madd_4_carry_4 ;
wire un7_square_madd_1_add4 ;
wire un7_square_madd_4_carry_3 ;
wire un7_square_madd_1_add3 ;
wire un7_square_madd_4_carry_2 ;
wire un7_square_madd_1_add2 ;
wire un7_square_madd_4_carry_1 ;
wire un7_square_madd_1_add1 ;
wire un7_square_madd_0_add2 ;
wire un7_square_madd_4_carry_0 ;
wire un7_square_madd_0_add1 ;
wire un7_square_madd_2_carry_7 ;
wire un7_square_madd_2_carry_6 ;
wire un7_square_madd_2_carry_3 ;
wire un7_square_madd_2_carry_2 ;
wire un7_square_madd_1_carry_7 ;
wire un7_square_madd_1_carry_6 ;
wire un7_square_madd_1_carry_5 ;
wire un7_square_madd_1_carry_4 ;
wire un7_square_madd_1_carry_3 ;
wire un7_square_madd_1_carry_2 ;
wire un7_square_madd_1_carry_1 ;
wire un7_square_madd_0_carry_6 ;
wire un7_square_madd_0_carry_5 ;
wire un7_square_madd_0_carry_4 ;
wire un7_square_madd_0_carry_3 ;
wire un7_square_madd_0_carry_2 ;
wire un7_square_madd_0_carry_1 ;
wire un2_square_madd_carry_10 ;
wire un2_square_madd_carry_9 ;
wire un2_square_madd_carry_8 ;
wire un2_square_madd_carry_7 ;
wire un2_square_madd_carry_6 ;
wire un2_square_madd_carry_5 ;
wire un2_square_madd_carry_4 ;
wire un2_square_madd_carry_3 ;
wire un2_square_madd_carry_2 ;
wire un2_square_madd_carry_1 ;
wire un2_square_madd_carry_0 ;
wire N_1 ;
wire N_2 ;
wire N_3 ;
wire N_4 ;
wire N_5 ;
wire N_6 ;
wire N_7 ;
wire N_8 ;
wire N_9 ;
//@1:1
  assign VCC = 1'b1;
//@1:1
  assign GND = 1'b0;
  cyclone_lcell un2_square_madd_4_add9_term (
	.combout(un2_square_madd_4[12]),
	.dataa(VCC),
	.datab(VCC),
	.datac(VCC),
	.datad(VCC),
	.aclr(GND),
	.sclr(GND),
	.sload(GND),
	.ena(VCC),
	.cin(un2_square_madd_4_add9_cout),
	.inverta(GND),
	.aload(GND),
	.regcascin(GND)
);
defparam un2_square_madd_4_add9_term.cin_used="true";
defparam un2_square_madd_4_add9_term.operation_mode="normal";
defparam un2_square_madd_4_add9_term.output_mode="comb_only";
defparam un2_square_madd_4_add9_term.lut_mask="f0f0";
defparam un2_square_madd_4_add9_term.synch_mode="off";
defparam un2_square_madd_4_add9_term.sum_lutc_input="cin";
  cyclone_lcell un2_square_madd_3_add8_term (
	.combout(un2_square_madd_3[15]),
	.dataa(VCC),
	.datab(VCC),
	.datac(VCC),
	.datad(VCC),
	.aclr(GND),
	.sclr(GND),
	.sload(GND),
	.ena(VCC),
	.cin(un2_square_madd_3_add8_cout),
	.inverta(GND),
	.aload(GND),
	.regcascin(GND)
);
defparam un2_square_madd_3_add8_term.cin_used="true";
defparam un2_square_madd_3_add8_term.operation_mode="normal";
defparam un2_square_madd_3_add8_term.output_mode="comb_only";
defparam un2_square_madd_3_add8_term.lut_mask="f0f0";
defparam un2_square_madd_3_add8_term.synch_mode="off";
defparam un2_square_madd_3_add8_term.sum_lutc_input="cin";
  cyclone_lcell un2_square_madd_3_add6_term (
	.combout(un2_square_madd_3[13]),
	.dataa(VCC),
	.datab(VCC),
	.datac(VCC),
	.datad(VCC),
	.aclr(GND),
	.sclr(GND),
	.sload(GND),
	.ena(VCC),
	.cin(un2_square_madd_3_add6_cout),
	.inverta(GND),
	.aload(GND),
	.regcascin(GND)
);
defparam un2_square_madd_3_add6_term.cin_used="true";
defparam un2_square_madd_3_add6_term.operation_mode="normal";
defparam un2_square_madd_3_add6_term.output_mode="comb_only";
defparam un2_square_madd_3_add6_term.lut_mask="f0f0";
defparam un2_square_madd_3_add6_term.synch_mode="off";
defparam un2_square_madd_3_add6_term.sum_lutc_input="cin";
  cyclone_lcell un2_square_madd_3_add2_term (
	.combout(un2_square_madd_3[9]),
	.dataa(VCC),
	.datab(VCC),
	.datac(VCC),
	.datad(VCC),
	.aclr(GND),
	.sclr(GND),
	.sload(GND),
	.ena(VCC),
	.cin(un2_square_madd_3_add2_cout),
	.inverta(GND),
	.aload(GND),
	.regcascin(GND)
);
defparam un2_square_madd_3_add2_term.cin_used="true";
defparam un2_square_madd_3_add2_term.operation_mode="normal";
defparam un2_square_madd_3_add2_term.output_mode="comb_only";
defparam un2_square_madd_3_add2_term.lut_mask="f0f0";
defparam un2_square_madd_3_add2_term.synch_mode="off";
defparam un2_square_madd_3_add2_term.sum_lutc_input="cin";
  cyclone_lcell un2_square_madd_2_add8_term (
	.combout(un2_square_madd_2[13]),
	.dataa(VCC),
	.datab(VCC),
	.datac(VCC),
	.datad(VCC),
	.aclr(GND),
	.sclr(GND),
	.sload(GND),
	.ena(VCC),
	.cin(un2_square_madd_2_add8_cout),
	.inverta(GND),
	.aload(GND),
	.regcascin(GND)
);
defparam un2_square_madd_2_add8_term.cin_used="true";
defparam un2_square_madd_2_add8_term.operation_mode="normal";
defparam un2_square_madd_2_add8_term.output_mode="comb_only";
defparam un2_square_madd_2_add8_term.lut_mask="f0f0";
defparam un2_square_madd_2_add8_term.synch_mode="off";
defparam un2_square_madd_2_add8_term.sum_lutc_input="cin";
  cyclone_lcell un2_square_madd_1_add8_term (
	.combout(un2_square_madd_1[11]),
	.dataa(VCC),
	.datab(VCC),
	.datac(VCC),
	.datad(VCC),
	.aclr(GND),
	.sclr(GND),
	.sload(GND),
	.ena(VCC),
	.cin(un2_square_madd_1_add8_cout),
	.inverta(GND),
	.aload(GND),
	.regcascin(GND)
);
defparam un2_square_madd_1_add8_term.cin_used="true";
defparam un2_square_madd_1_add8_term.operation_mode="normal";
defparam un2_square_madd_1_add8_term.output_mode="comb_only";
defparam un2_square_madd_1_add8_term.lut_mask="f0f0";
defparam un2_square_madd_1_add8_term.synch_mode="off";
defparam un2_square_madd_1_add8_term.sum_lutc_input="cin";
  cyclone_lcell un2_square_madd_0_add7_term (
	.combout(un2_square_madd_0[9]),
	.dataa(VCC),
	.datab(VCC),
	.datac(VCC),
	.datad(VCC),
	.aclr(GND),
	.sclr(GND),
	.sload(GND),
	.ena(VCC),
	.cin(un2_square_madd_0_add7_cout),
	.inverta(GND),
	.aload(GND),
	.regcascin(GND)
);
defparam un2_square_madd_0_add7_term.cin_used="true";
defparam un2_square_madd_0_add7_term.operation_mode="normal";
defparam un2_square_madd_0_add7_term.output_mode="comb_only";
defparam un2_square_madd_0_add7_term.lut_mask="f0f0";
defparam un2_square_madd_0_add7_term.synch_mode="off";
defparam un2_square_madd_0_add7_term.sum_lutc_input="cin";
  cyclone_lcell un7_square_madd_4_add9_term (
	.combout(un7_square_madd_4[12]),
	.dataa(VCC),