smbus_timesim.vhd

可编程器件厂商Xilinx的用于设计SMBus 控制器的源程序

  signal uc_ctrl_mal_bit_reset_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mal_bit_reset_MC_D : STD_LOGIC; 
  signal uc_ctrl_mal_bit_reset_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mal_bit_reset_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mal_bit_reset_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mal_bit_reset_MC_D2_PT_2 : STD_LOGIC; 
  signal uc_ctrl_mal_bit_reset_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mal_bit_reset_MC_D_TFF : STD_LOGIC; 
  signal N1102_MC_Q : STD_LOGIC; 
  signal N1102_MC_D : STD_LOGIC; 
  signal N1102_MC_D1 : STD_LOGIC; 
  signal N1102_MC_D2_PT_0 : STD_LOGIC; 
  signal N1102_MC_D2_PT_1 : STD_LOGIC; 
  signal N1102_MC_D2_PT_2 : STD_LOGIC; 
  signal smbus_ctrl_bus_busy_d1 : STD_LOGIC; 
  signal N1102_MC_D2_PT_3 : STD_LOGIC; 
  signal N1102_MC_D2_PT_4 : STD_LOGIC; 
  signal N1102_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_bus_busy_d1_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_bus_busy_d1_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_bus_busy_d1_MC_D : STD_LOGIC; 
  signal smbus_ctrl_bus_busy_d1_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_bus_busy_d1_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_bus_busy_d1_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_maas_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_maas_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_maas_MC_D : STD_LOGIC; 
  signal smbus_ctrl_maas_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_maas_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_maas_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_detect_stop_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_detect_stop_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_detect_stop_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_bus_busy_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_bus_busy_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_bus_busy_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_scl_out_reg_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_scl_out_reg_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_scl_out_reg_MC_D2_PT_1 : STD_LOGIC; 
  signal smbus_ctrl_scl_out_reg_MC_D2 : STD_LOGIC; 
  signal N1323_MC_Q : STD_LOGIC; 
  signal N1323_MC_D : STD_LOGIC; 
  signal N1323_MC_D1 : STD_LOGIC; 
  signal N1323_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_slave_sda : STD_LOGIC; 
  signal N1323_MC_D2_PT_1 : STD_LOGIC; 
  signal N1323_MC_D2_PT_2 : STD_LOGIC; 
  signal N1323_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_slave_sda_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_slave_sda_MC_D : STD_LOGIC; 
  signal smbus_ctrl_slave_sda_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_slave_sda_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_slave_sda_MC_D2_PT_1 : STD_LOGIC; 
  signal smbus_ctrl_slave_sda_MC_D2_PT_2 : STD_LOGIC; 
  signal smbus_ctrl_slave_sda_MC_D2 : STD_LOGIC; 
  signal N913_MC_Q : STD_LOGIC; 
  signal N913_MC_D : STD_LOGIC; 
  signal N913_MC_D1 : STD_LOGIC; 
  signal N913_MC_D2_PT_0 : STD_LOGIC; 
  signal N913_MC_D2_PT_1 : STD_LOGIC; 
  signal N913_MC_D2 : STD_LOGIC; 
  signal data_bus_0_MC_D1 : STD_LOGIC; 
  signal data_bus_0_MC_UIM : STD_LOGIC; 
  signal N_PZ_627 : STD_LOGIC; 
  signal data_bus_0_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_0 : STD_LOGIC; 
  signal data_bus_0_MC_D2_PT_1 : STD_LOGIC; 
  signal smbus_ctrl_rxak : STD_LOGIC; 
  signal data_bus_0_MC_D2_PT_2 : STD_LOGIC; 
  signal uc_ctrl_madr_0 : STD_LOGIC; 
  signal data_bus_0_MC_D2_PT_3 : STD_LOGIC; 
  signal data_bus_0_MC_D2 : STD_LOGIC; 
  signal data_bus_0_MC_BUFOE_OUT : STD_LOGIC; 
  signal FOOBAR3_ctinst_7 : STD_LOGIC; 
  signal N_PZ_627_MC_Q : STD_LOGIC; 
  signal N_PZ_627_MC_D : STD_LOGIC; 
  signal N_PZ_627_MC_D1 : STD_LOGIC; 
  signal N_PZ_627_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_627_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_627_MC_D2_PT_2 : STD_LOGIC; 
  signal N_PZ_627_MC_D2_PT_3 : STD_LOGIC; 
  signal N_PZ_627_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_0_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_0_MC_D : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_0_MC_CE : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_0_MC_CE_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_0_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_0_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_0_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_rxak_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_rxak_MC_D : STD_LOGIC; 
  signal smbus_ctrl_rxak_MC_CE : STD_LOGIC; 
  signal smbus_ctrl_rxak_MC_CE_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_rxak_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_rxak_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_rxak_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_madr_0_MC_Q : STD_LOGIC; 
  signal uc_ctrl_madr_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_madr_0_MC_D : STD_LOGIC; 
  signal uc_ctrl_madr_0_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_madr_0_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_madr_0_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_madr_0_MC_D2 : STD_LOGIC; 
  signal data_bus_1_MC_Q : STD_LOGIC; 
  signal data_bus_1_MC_OE : STD_LOGIC; 
  signal data_bus_1_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_bus_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_bus_1_MC_D : STD_LOGIC; 
  signal data_bus_1_MC_D1 : STD_LOGIC; 
  signal data_bus_1_MC_UIM : STD_LOGIC; 
  signal data_bus_1_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_1 : STD_LOGIC; 
  signal data_bus_1_MC_D2_PT_1 : STD_LOGIC; 
  signal smbus_ctrl_mif : STD_LOGIC; 
  signal data_bus_1_MC_D2_PT_2 : STD_LOGIC; 
  signal data_bus_1_MC_D2_PT_3 : STD_LOGIC; 
  signal data_bus_1_MC_D2 : STD_LOGIC; 
  signal data_bus_1_MC_BUFOE_OUT : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_1_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_1_MC_D : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_1_MC_CE : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_1_MC_CE_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_1_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_1_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_1_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_mif_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_mif_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_mif_MC_D : STD_LOGIC; 
  signal smbus_ctrl_mif_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mif_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_mif_MC_D2 : STD_LOGIC; 
  signal data_bus_2_MC_Q : STD_LOGIC; 
  signal data_bus_2_MC_OE : STD_LOGIC; 
  signal data_bus_2_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_bus_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_bus_2_MC_D : STD_LOGIC; 
  signal data_bus_2_MC_D1 : STD_LOGIC; 
  signal data_bus_2_MC_UIM : STD_LOGIC; 
  signal data_bus_2_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_2 : STD_LOGIC; 
  signal data_bus_2_MC_D2_PT_1 : STD_LOGIC; 
  signal smbus_ctrl_srw : STD_LOGIC; 
  signal data_bus_2_MC_D2_PT_2 : STD_LOGIC; 
  signal data_bus_2_MC_D2_PT_3 : STD_LOGIC; 
  signal data_bus_2_MC_D2_PT_4 : STD_LOGIC; 
  signal data_bus_2_MC_D2 : STD_LOGIC; 
  signal data_bus_2_MC_BUFOE_OUT : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_2_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_2_MC_D : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_2_MC_CE : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_2_MC_CE_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_2_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_2_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_2_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_srw_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_srw_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_srw_MC_D : STD_LOGIC; 
  signal smbus_ctrl_srw_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_srw_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_srw_MC_D2 : STD_LOGIC; 
  signal data_bus_3_MC_Q : STD_LOGIC; 
  signal data_bus_3_MC_OE : STD_LOGIC; 
  signal data_bus_3_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_bus_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_bus_3_MC_D : STD_LOGIC; 
  signal data_bus_3_MC_D1 : STD_LOGIC; 
  signal data_bus_3_MC_UIM : STD_LOGIC; 
  signal data_bus_3_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_3 : STD_LOGIC; 
  signal data_bus_3_MC_D2_PT_1 : STD_LOGIC; 
  signal data_bus_3_MC_D2_PT_2 : STD_LOGIC; 
  signal data_bus_3_MC_D2_PT_3 : STD_LOGIC; 
  signal data_bus_3_MC_D2 : STD_LOGIC; 
  signal data_bus_3_MC_BUFOE_OUT : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_3_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_3_MC_D : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_3_MC_CE : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_3_MC_CE_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_3_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_3_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_3_MC_D2 : STD_LOGIC; 
  signal data_bus_4_MC_Q : STD_LOGIC; 
  signal data_bus_4_MC_OE : STD_LOGIC; 
  signal data_bus_4_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_bus_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_bus_4_MC_D : STD_LOGIC; 
  signal data_bus_4_MC_D1 : STD_LOGIC; 
  signal data_bus_4_MC_UIM : STD_LOGIC; 
  signal data_bus_4_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_4 : STD_LOGIC; 
  signal data_bus_4_MC_D2_PT_1 : STD_LOGIC; 
  signal data_bus_4_MC_D2_PT_2 : STD_LOGIC; 
  signal data_bus_4_MC_D2_PT_3 : STD_LOGIC; 
  signal data_bus_4_MC_D2_PT_4 : STD_LOGIC; 
  signal data_bus_4_MC_D2 : STD_LOGIC; 
  signal data_bus_4_MC_BUFOE_OUT : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_4_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_4_MC_D : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_4_MC_CE : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_4_MC_CE_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_4_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_4_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_4_MC_D2 : STD_LOGIC; 
  signal data_bus_5_MC_Q : STD_LOGIC; 
  signal data_bus_5_MC_OE : STD_LOGIC; 
  signal data_bus_5_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_bus_5_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_bus_5_MC_D : STD_LOGIC; 
  signal data_bus_5_MC_D1 : STD_LOGIC; 
  signal data_bus_5_MC_UIM : STD_LOGIC; 
  signal data_bus_5_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_5 : STD_LOGIC; 
  signal data_bus_5_MC_D2_PT_1 : STD_LOGIC; 
  signal data_bus_5_MC_D2_PT_2 : STD_LOGIC; 
  signal data_bus_5_MC_D2_PT_3 : STD_LOGIC; 
  signal data_bus_5_MC_D2_PT_4 : STD_LOGIC; 
  signal data_bus_5_MC_D2 : STD_LOGIC; 
  signal data_bus_5_MC_BUFOE_OUT : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_5_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_5_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_5_MC_D : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_5_MC_CE : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_5_MC_CE_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_5_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_5_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_5_MC_D2 : STD_LOGIC; 
  signal data_bus_6_MC_Q : STD_LOGIC; 
  signal data_bus_6_MC_OE : STD_LOGIC; 
  signal data_bus_6_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_bus_6_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_bus_6_MC_D : STD_LOGIC; 
  signal data_bus_6_MC_D1 : STD_LOGIC; 
  signal data_bus_6_MC_UIM : STD_LOGIC; 
  signal data_bus_6_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_6 : STD_LOGIC; 
  signal data_bus_6_MC_D2_PT_1 : STD_LOGIC; 
  signal data_bus_6_MC_D2_PT_2 : STD_LOGIC; 
  signal uc_ctrl_mien : STD_LOGIC; 
  signal data_bus_6_MC_D2_PT_3 : STD_LOGIC; 
  signal data_bus_6_MC_D2_PT_4 : STD_LOGIC; 
  signal data_bus_6_MC_D2 : STD_LOGIC; 
  signal data_bus_6_MC_BUFOE_OUT : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_6_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_6_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_6_MC_D : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_6_MC_CE : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_6_MC_CE_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_6_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_6_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_6_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mien_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mien_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mien_MC_D : STD_LOGIC; 
  signal uc_ctrl_mien_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mien_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mien_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mien_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mien_MC_D_TFF : STD_LOGIC; 
  signal data_bus_7_MC_Q : STD_LOGIC; 
  signal data_bus_7_MC_OE : STD_LOGIC; 
  signal data_bus_7_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_bus_7_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_bus_7_MC_D : STD_LOGIC; 
  signal data_bus_7_MC_D1 : STD_LOGIC; 
  signal data_bus_7_MC_UIM : STD_LOGIC; 
  signal data_bus_7_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_7 : STD_LOGIC; 
  signal data_bus_7_MC_D2_PT_1 : STD_LOGIC; 
  signal data_bus_7_MC_D2_PT_2 : STD_LOGIC; 
  signal data_bus_7_MC_D2_PT_3 : STD_LOGIC; 
  signal data_bus_7_MC_D2_PT_4 : STD_LOGIC; 
  signal data_bus_7_MC_D2 : STD_LOGIC; 
  signal data_bus_7_MC_BUFOE_OUT : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_7_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_7_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_7_MC_D : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_7_MC_CE : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_7_MC_CE_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_7_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_7_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_mbdr_smbus_7_MC_D2 : STD_LOGIC; 
  signal irq_MC_Q : STD_LOGIC; 
  signal irq_MC_OE : STD_LOGIC; 
  signal irq_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal irq_MC_D : STD_LOGIC; 
  signal irq_MC_D1 : STD_LOGIC; 
  signal irq_MC_D2 : STD_LOGIC; 
  signal irq_MC_BUFOE_OUT : STD_LOGIC; 
  signal FOOBAR11_ctinst_0 : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal PRLD : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR1_ctinst_0_OUT : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR1_ctinst_2_OUT : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR4_ctinst_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR4_ctinst_0_OUT : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR4_ctinst_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR4_ctinst_7_OUT : STD_L