smbus_timesim.vhd

来自「可编程器件厂商Xilinx的用于设计SMBus 控制器的源程序」· VHDL 代码 · 共 1,523 行 · 第 1/5 页

  signal uc_ctrl_msta : STD_LOGIC; 
  signal smbus_ctrl_master_slave_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_master_slave_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_master_slave_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_msta_MC_Q : STD_LOGIC; 
  signal uc_ctrl_msta_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_msta_MC_D : STD_LOGIC; 
  signal uc_ctrl_msta_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_msta_rst : STD_LOGIC; 
  signal uc_ctrl_msta_MC_D2_PT_0 : STD_LOGIC; 
  signal data_bus_5_II_UIM : STD_LOGIC; 
  signal uc_ctrl_msta_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_msta_MC_D2_PT_2 : STD_LOGIC; 
  signal uc_ctrl_msta_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_msta_MC_D_TFF : STD_LOGIC; 
  signal smbus_ctrl_msta_rst_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_msta_rst_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_msta_rst_MC_D : STD_LOGIC; 
  signal smbus_ctrl_msta_rst_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_msta_rst_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_msta_rst_MC_D2_PT_1 : STD_LOGIC; 
  signal smbus_ctrl_msta_rst_MC_D2_PT_2 : STD_LOGIC; 
  signal smbus_ctrl_msta_rst_MC_D2_PT_3 : STD_LOGIC; 
  signal smbus_ctrl_msta_rst_MC_D2_PT_4 : STD_LOGIC; 
  signal smbus_ctrl_msta_rst_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_sda_out_reg_d1_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_sda_out_reg_d1_MC_D : STD_LOGIC; 
  signal smbus_ctrl_sda_out_reg_d1_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_sda_out_reg : STD_LOGIC; 
  signal smbus_ctrl_sda_out_reg_d1_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_sda_out_reg_d1_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_sda_out_reg_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_sda_out_reg_MC_D : STD_LOGIC; 
  signal smbus_ctrl_sda_out_reg_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_sda_out_reg_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_sda_out_reg_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_sda_out_reg_MC_D2_PT_1 : STD_LOGIC; 
  signal smbus_ctrl_sda_out_reg_MC_D2_PT_2 : STD_LOGIC; 
  signal smbus_ctrl_sda_out_reg_MC_D2_PT_3 : STD_LOGIC; 
  signal smbus_ctrl_sda_out_reg_MC_D2_PT_4 : STD_LOGIC; 
  signal smbus_ctrl_gen_stop : STD_LOGIC; 
  signal smbus_ctrl_sda_out_reg_MC_D2_PT_5 : STD_LOGIC; 
  signal smbus_ctrl_sm_stop : STD_LOGIC; 
  signal smbus_ctrl_sda_out_reg_MC_D2_PT_6 : STD_LOGIC; 
  signal smbus_ctrl_sda_out_reg_MC_D2_PT_7 : STD_LOGIC; 
  signal smbus_ctrl_master_sda : STD_LOGIC; 
  signal smbus_ctrl_sda_out_reg_MC_D2_PT_8 : STD_LOGIC; 
  signal smbus_ctrl_sda_out_reg_MC_D2_PT_9 : STD_LOGIC; 
  signal smbus_ctrl_sda_out_reg_MC_D2_PT_10 : STD_LOGIC; 
  signal smbus_ctrl_sda_out_reg_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_rep_start_det_reg_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_rep_start_det_reg_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_rep_start_det_reg_MC_D : STD_LOGIC; 
  signal smbus_ctrl_rep_start_det_reg_MC_D1 : STD_LOGIC; 
  signal N2154 : STD_LOGIC; 
  signal smbus_ctrl_rep_start_det_reg_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_rep_start_det_reg_MC_D2_PT_1 : STD_LOGIC; 
  signal smbus_ctrl_rep_start_det_reg_MC_D2 : STD_LOGIC; 
  signal N2154_MC_Q : STD_LOGIC; 
  signal N2154_MC_D : STD_LOGIC; 
  signal N2154_MC_D1 : STD_LOGIC; 
  signal N2154_MC_D2_PT_0 : STD_LOGIC; 
  signal N2154_MC_D2_PT_1 : STD_LOGIC; 
  signal N2154_MC_D2 : STD_LOGIC; 
  signal N574_MC_Q : STD_LOGIC; 
  signal N574_MC_R_OR_PRLD : STD_LOGIC; 
  signal N574_MC_D : STD_LOGIC; 
  signal N574_MC_D1 : STD_LOGIC; 
  signal N574_MC_D2_PT_0 : STD_LOGIC; 
  signal N574_MC_D2_PT_1 : STD_LOGIC; 
  signal N574_MC_D2_PT_2 : STD_LOGIC; 
  signal N574_MC_D2 : STD_LOGIC; 
  signal N574_MC_D_TFF : STD_LOGIC; 
  signal N_PZ_653_MC_Q : STD_LOGIC; 
  signal N_PZ_653_MC_D : STD_LOGIC; 
  signal N_PZ_653_MC_D1 : STD_LOGIC; 
  signal N_PZ_653_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_653_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_653_MC_D2_PT_2 : STD_LOGIC; 
  signal N_PZ_653_MC_D2 : STD_LOGIC; 
  signal N571_MC_Q : STD_LOGIC; 
  signal N571_MC_R_OR_PRLD : STD_LOGIC; 
  signal N571_MC_D : STD_LOGIC; 
  signal N571_MC_D1 : STD_LOGIC; 
  signal N571_MC_D2_PT_0 : STD_LOGIC; 
  signal N571_MC_D2_PT_1 : STD_LOGIC; 
  signal N571_MC_D2_PT_2 : STD_LOGIC; 
  signal N571_MC_D2 : STD_LOGIC; 
  signal N571_MC_D_TFF : STD_LOGIC; 
  signal N_PZ_657_MC_Q : STD_LOGIC; 
  signal N_PZ_657_MC_D : STD_LOGIC; 
  signal N_PZ_657_MC_D1 : STD_LOGIC; 
  signal N_PZ_657_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_657_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_657_MC_D2 : STD_LOGIC; 
  signal N583_MC_Q : STD_LOGIC; 
  signal N583_MC_R_OR_PRLD : STD_LOGIC; 
  signal N583_MC_D : STD_LOGIC; 
  signal N583_MC_D1 : STD_LOGIC; 
  signal N583_MC_D2_PT_0 : STD_LOGIC; 
  signal N583_MC_D2_PT_1 : STD_LOGIC; 
  signal N583_MC_D2 : STD_LOGIC; 
  signal N583_MC_D_TFF : STD_LOGIC; 
  signal N580_MC_Q : STD_LOGIC; 
  signal N580_MC_R_OR_PRLD : STD_LOGIC; 
  signal N580_MC_D : STD_LOGIC; 
  signal N580_MC_D1 : STD_LOGIC; 
  signal N580_MC_D2_PT_0 : STD_LOGIC; 
  signal N580_MC_D2_PT_1 : STD_LOGIC; 
  signal N580_MC_D2_PT_2 : STD_LOGIC; 
  signal N580_MC_D2 : STD_LOGIC; 
  signal N580_MC_D_TFF : STD_LOGIC; 
  signal N751_MC_Q : STD_LOGIC; 
  signal N751_MC_R_OR_PRLD : STD_LOGIC; 
  signal N751_MC_D : STD_LOGIC; 
  signal N751_MC_D1 : STD_LOGIC; 
  signal N751_MC_D2_PT_0 : STD_LOGIC; 
  signal N751_MC_D2_PT_1 : STD_LOGIC; 
  signal N751_MC_D2_PT_2 : STD_LOGIC; 
  signal N751_MC_D2 : STD_LOGIC; 
  signal N751_MC_D_TFF : STD_LOGIC; 
  signal N749_MC_Q : STD_LOGIC; 
  signal N749_MC_R_OR_PRLD : STD_LOGIC; 
  signal N749_MC_D : STD_LOGIC; 
  signal N749_MC_D1 : STD_LOGIC; 
  signal N749_MC_D2_PT_0 : STD_LOGIC; 
  signal N749_MC_D2_PT_1 : STD_LOGIC; 
  signal N749_MC_D2_PT_2 : STD_LOGIC; 
  signal N749_MC_D2 : STD_LOGIC; 
  signal N749_MC_D_TFF : STD_LOGIC; 
  signal N589_MC_Q : STD_LOGIC; 
  signal N589_MC_R_OR_PRLD : STD_LOGIC; 
  signal N589_MC_D : STD_LOGIC; 
  signal N589_MC_D1 : STD_LOGIC; 
  signal N589_MC_D2_PT_0 : STD_LOGIC; 
  signal N589_MC_D2_PT_1 : STD_LOGIC; 
  signal N589_MC_D2 : STD_LOGIC; 
  signal N589_MC_D_TFF : STD_LOGIC; 
  signal N586_MC_Q : STD_LOGIC; 
  signal N586_MC_R_OR_PRLD : STD_LOGIC; 
  signal N586_MC_D : STD_LOGIC; 
  signal N586_MC_D1 : STD_LOGIC; 
  signal N586_MC_D2_PT_0 : STD_LOGIC; 
  signal N586_MC_D2_PT_1 : STD_LOGIC; 
  signal N586_MC_D2 : STD_LOGIC; 
  signal N586_MC_D_TFF : STD_LOGIC; 
  signal N577_MC_Q : STD_LOGIC; 
  signal N577_MC_R_OR_PRLD : STD_LOGIC; 
  signal N577_MC_D : STD_LOGIC; 
  signal N577_MC_D1 : STD_LOGIC; 
  signal N577_MC_D2_PT_0 : STD_LOGIC; 
  signal N577_MC_D2_PT_1 : STD_LOGIC; 
  signal N577_MC_D2_PT_2 : STD_LOGIC; 
  signal N577_MC_D2 : STD_LOGIC; 
  signal N577_MC_D_TFF : STD_LOGIC; 
  signal N_PZ_734_MC_Q : STD_LOGIC; 
  signal N_PZ_734_MC_D : STD_LOGIC; 
  signal N_PZ_734_MC_D1 : STD_LOGIC; 
  signal N_PZ_734_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_stop_scl_reg : STD_LOGIC; 
  signal N_PZ_734_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_734_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_rsta_MC_Q : STD_LOGIC; 
  signal uc_ctrl_rsta_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_rsta_MC_D : STD_LOGIC; 
  signal uc_ctrl_rsta_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_rsta_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_rsta_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_rsta_MC_D2_PT_2 : STD_LOGIC; 
  signal uc_ctrl_rsta_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_rsta_MC_D_TFF : STD_LOGIC; 
  signal smbus_ctrl_stop_scl_reg_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_stop_scl_reg_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_stop_scl_reg_MC_D : STD_LOGIC; 
  signal smbus_ctrl_stop_scl_reg_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_stop_scl_reg_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_stop_scl_reg_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_stop_scl_reg_MC_D2_PT_1 : STD_LOGIC; 
  signal smbus_ctrl_stop_scl_reg_MC_D2_PT_2 : STD_LOGIC; 
  signal smbus_ctrl_stop_scl_reg_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_gen_stop_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_gen_stop_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_gen_stop_MC_D : STD_LOGIC; 
  signal smbus_ctrl_gen_stop_MC_CE : STD_LOGIC; 
  signal N1077 : STD_LOGIC; 
  signal smbus_ctrl_gen_stop_MC_CE_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_msta_d1 : STD_LOGIC; 
  signal smbus_ctrl_gen_stop_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_gen_stop_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_gen_stop_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_msta_d1_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_msta_d1_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_msta_d1_MC_D : STD_LOGIC; 
  signal smbus_ctrl_msta_d1_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_msta_d1_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_msta_d1_MC_D2 : STD_LOGIC; 
  signal N1077_MC_Q : STD_LOGIC; 
  signal N1077_MC_D : STD_LOGIC; 
  signal N1077_MC_D1 : STD_LOGIC; 
  signal N1077_MC_D2_PT_0 : STD_LOGIC; 
  signal N1077_MC_D2_PT_1 : STD_LOGIC; 
  signal N1077_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_sm_stop_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_sm_stop_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_sm_stop_MC_D : STD_LOGIC; 
  signal smbus_ctrl_sm_stop_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_sm_stop_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_sm_stop_MC_D2_PT_1 : STD_LOGIC; 
  signal smbus_ctrl_sm_stop_MC_D2_PT_2 : STD_LOGIC; 
  signal smbus_ctrl_sm_stop_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_sm_stop_MC_D_TFF : STD_LOGIC; 
  signal smbus_ctrl_master_sda_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_master_sda_MC_D : STD_LOGIC; 
  signal smbus_ctrl_master_sda_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_txak : STD_LOGIC; 
  signal smbus_ctrl_master_sda_MC_D2_PT_0 : STD_LOGIC; 
  signal N998 : STD_LOGIC; 
  signal smbus_ctrl_master_sda_MC_D2_PT_1 : STD_LOGIC; 
  signal smbus_ctrl_master_sda_MC_D2_PT_2 : STD_LOGIC; 
  signal smbus_ctrl_master_sda_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_txak_MC_Q : STD_LOGIC; 
  signal uc_ctrl_txak_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_txak_MC_D : STD_LOGIC; 
  signal uc_ctrl_txak_MC_D1 : STD_LOGIC; 
  signal data_bus_3_II_UIM : STD_LOGIC; 
  signal uc_ctrl_txak_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_txak_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_txak_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_txak_MC_D_TFF : STD_LOGIC; 
  signal N998_MC_Q : STD_LOGIC; 
  signal N998_MC_R_OR_PRLD : STD_LOGIC; 
  signal N998_MC_D : STD_LOGIC; 
  signal N998_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_shift_reg_ld : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_7 : STD_LOGIC; 
  signal N998_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_shift_reg_en : STD_LOGIC; 
  signal N1330 : STD_LOGIC; 
  signal N998_MC_D2_PT_1 : STD_LOGIC; 
  signal N998_MC_D2_PT_2 : STD_LOGIC; 
  signal N998_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_shift_reg_ld_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_shift_reg_ld_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_shift_reg_ld_MC_D : STD_LOGIC; 
  signal smbus_ctrl_shift_reg_ld_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_shift_reg_ld_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_shift_reg_ld_MC_D2_PT_1 : STD_LOGIC; 
  signal smbus_ctrl_shift_reg_ld_MC_D2_PT_2 : STD_LOGIC; 
  signal smbus_ctrl_shift_reg_ld_MC_D2_PT_3 : STD_LOGIC; 
  signal smbus_ctrl_shift_reg_ld_MC_D2_PT_4 : STD_LOGIC; 
  signal smbus_ctrl_shift_reg_ld_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mtx_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mtx_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mtx_MC_D : STD_LOGIC; 
  signal uc_ctrl_mtx_MC_D1 : STD_LOGIC; 
  signal data_bus_4_II_UIM : STD_LOGIC; 
  signal uc_ctrl_mtx_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mtx_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mtx_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mtx_MC_D_TFF : STD_LOGIC; 
  signal N1051_MC_Q : STD_LOGIC; 
  signal N1051_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1051_MC_D : STD_LOGIC; 
  signal FOOBAR7_ctinst_4 : STD_LOGIC; 
  signal smbus_ctrl_smbus_header_en : STD_LOGIC; 
  signal smbus_ctrl_smbus_header_en_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_smbus_header_en_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_smbus_header_en_MC_D : STD_LOGIC; 
  signal smbus_ctrl_smbus_header_en_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_smbus_header_en_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_smbus_header_en_MC_D2_PT_1 : STD_LOGIC; 
  signal smbus_ctrl_smbus_header_en_MC_D2 : STD_LOGIC; 
  signal N1051_MC_D1_PT_0 : STD_LOGIC; 
  signal N1051_MC_D1 : STD_LOGIC; 
  signal N1051_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_7_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_7_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_7_MC_D : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_7_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_data_en : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_7_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_7_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_7_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_7_MC_D_TFF : STD_LOGIC; 
  signal uc_ctrl_data_en_MC_Q : STD_LOGIC; 
  signal uc_ctrl_data_en_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_data_en_MC_D : STD_LOGIC; 
  signal uc_ctrl_data_en_MC_D1_PT_0 : STD_LOGIC; 
  signal uc_ctrl_data_en_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_data_en_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_shift_reg_en_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_shift_reg_en_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_shift_reg_en_MC_D : STD_LOGIC; 
  signal smbus_ctrl_shift_reg_en_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_shift_reg_en_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_shift_reg_en_MC_D2_PT_1 : STD_LOGIC; 
  signal smbus_ctrl_shift_reg_en_MC_D2_PT_2 : STD_LOGIC; 
  signal smbus_ctrl_shift_reg_en_MC_D2 : STD_LOGIC; 
  signal N1330_MC_Q : STD_LOGIC; 
  signal N1330_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1330_MC_D : STD_LOGIC; 
  signal N1330_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_6 : STD_LOGIC; 
  signal N1330_MC_D2_PT_0 : STD_LOGIC; 
  signal N1329 : STD_LOGIC;