smbus_timesim.vhd

可编程器件厂商Xilinx的用于设计SMBus 控制器的源程序

  signal N1330_MC_D2_PT_1 : STD_LOGIC; 
  signal N1330_MC_D2_PT_2 : STD_LOGIC; 
  signal N1330_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_6_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_6_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_6_MC_D : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_6_MC_D1 : STD_LOGIC; 
  signal data_bus_6_II_UIM : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_6_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_6_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_6_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_6_MC_D_TFF : STD_LOGIC; 
  signal N1329_MC_Q : STD_LOGIC; 
  signal N1329_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1329_MC_D : STD_LOGIC; 
  signal N1329_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_5 : STD_LOGIC; 
  signal N1329_MC_D2_PT_0 : STD_LOGIC; 
  signal N1328 : STD_LOGIC; 
  signal N1329_MC_D2_PT_1 : STD_LOGIC; 
  signal N1329_MC_D2_PT_2 : STD_LOGIC; 
  signal N1329_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_5_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_5_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_5_MC_D : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_5_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_5_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_5_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_5_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_5_MC_D_TFF : STD_LOGIC; 
  signal N1328_MC_Q : STD_LOGIC; 
  signal N1328_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1328_MC_D : STD_LOGIC; 
  signal N1328_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_4 : STD_LOGIC; 
  signal N1328_MC_D2_PT_0 : STD_LOGIC; 
  signal N1327 : STD_LOGIC; 
  signal N1328_MC_D2_PT_1 : STD_LOGIC; 
  signal N1328_MC_D2_PT_2 : STD_LOGIC; 
  signal N1328_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_4_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_4_MC_D : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_4_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_4_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_4_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_4_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_4_MC_D_TFF : STD_LOGIC; 
  signal N1327_MC_Q : STD_LOGIC; 
  signal N1327_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1327_MC_D : STD_LOGIC; 
  signal N1327_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_3 : STD_LOGIC; 
  signal N1327_MC_D2_PT_0 : STD_LOGIC; 
  signal N1326 : STD_LOGIC; 
  signal N1327_MC_D2_PT_1 : STD_LOGIC; 
  signal N1327_MC_D2_PT_2 : STD_LOGIC; 
  signal N1327_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_3_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_3_MC_D : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_3_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_3_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_3_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_3_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_3_MC_D_TFF : STD_LOGIC; 
  signal N1326_MC_Q : STD_LOGIC; 
  signal N1326_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1326_MC_D : STD_LOGIC; 
  signal N1326_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_2 : STD_LOGIC; 
  signal N1326_MC_D2_PT_0 : STD_LOGIC; 
  signal N1325 : STD_LOGIC; 
  signal N1326_MC_D2_PT_1 : STD_LOGIC; 
  signal N1326_MC_D2_PT_2 : STD_LOGIC; 
  signal N1326_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_2_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_2_MC_D : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_2_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_2_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_2_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_2_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_2_MC_D_TFF : STD_LOGIC; 
  signal N1325_MC_Q : STD_LOGIC; 
  signal N1325_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1325_MC_D : STD_LOGIC; 
  signal N1325_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_1 : STD_LOGIC; 
  signal N1325_MC_D2_PT_0 : STD_LOGIC; 
  signal N1324 : STD_LOGIC; 
  signal N1325_MC_D2_PT_1 : STD_LOGIC; 
  signal N1325_MC_D2_PT_2 : STD_LOGIC; 
  signal N1325_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_1_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_1_MC_D : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_1_MC_D1 : STD_LOGIC; 
  signal data_bus_1_II_UIM : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_1_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_1_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_1_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_1_MC_D_TFF : STD_LOGIC; 
  signal N1324_MC_Q : STD_LOGIC; 
  signal N1324_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1324_MC_D : STD_LOGIC; 
  signal N1324_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_0 : STD_LOGIC; 
  signal N1324_MC_D2_PT_0 : STD_LOGIC; 
  signal N1324_MC_D2_PT_1 : STD_LOGIC; 
  signal N1324_MC_D2_PT_2 : STD_LOGIC; 
  signal N1324_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_0_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_0_MC_D : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_0_MC_D1 : STD_LOGIC; 
  signal data_bus_0_II_UIM : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_0_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_0_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_0_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_0_MC_D_TFF : STD_LOGIC; 
  signal smbus_ctrl_gen_start_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_gen_start_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_gen_start_MC_D : STD_LOGIC; 
  signal smbus_ctrl_gen_start_MC_CE : STD_LOGIC; 
  signal N1074 : STD_LOGIC; 
  signal smbus_ctrl_gen_start_MC_CE_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_gen_start_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_gen_start_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_gen_start_MC_D2 : STD_LOGIC; 
  signal N1074_MC_Q : STD_LOGIC; 
  signal N1074_MC_D : STD_LOGIC; 
  signal N1074_MC_D1 : STD_LOGIC; 
  signal N1074_MC_D2_PT_0 : STD_LOGIC; 
  signal N1074_MC_D2_PT_1 : STD_LOGIC; 
  signal N1074_MC_D2 : STD_LOGIC; 
  signal N400_MC_Q : STD_LOGIC; 
  signal N400_MC_D : STD_LOGIC; 
  signal N400_MC_D1 : STD_LOGIC; 
  signal N1334 : STD_LOGIC; 
  signal uc_ctrl_madr_1 : STD_LOGIC; 
  signal N400_MC_D2_PT_0 : STD_LOGIC; 
  signal N400_MC_D2_PT_1 : STD_LOGIC; 
  signal N1335 : STD_LOGIC; 
  signal uc_ctrl_madr_2 : STD_LOGIC; 
  signal N400_MC_D2_PT_2 : STD_LOGIC; 
  signal N400_MC_D2_PT_3 : STD_LOGIC; 
  signal N1336 : STD_LOGIC; 
  signal uc_ctrl_madr_3 : STD_LOGIC; 
  signal N400_MC_D2_PT_4 : STD_LOGIC; 
  signal N400_MC_D2_PT_5 : STD_LOGIC; 
  signal N1337 : STD_LOGIC; 
  signal uc_ctrl_madr_4 : STD_LOGIC; 
  signal N400_MC_D2_PT_6 : STD_LOGIC; 
  signal N400_MC_D2_PT_7 : STD_LOGIC; 
  signal N1338 : STD_LOGIC; 
  signal uc_ctrl_madr_5 : STD_LOGIC; 
  signal N400_MC_D2_PT_8 : STD_LOGIC; 
  signal N400_MC_D2_PT_9 : STD_LOGIC; 
  signal N1339 : STD_LOGIC; 
  signal uc_ctrl_madr_6 : STD_LOGIC; 
  signal N400_MC_D2_PT_10 : STD_LOGIC; 
  signal N400_MC_D2_PT_11 : STD_LOGIC; 
  signal N1340 : STD_LOGIC; 
  signal uc_ctrl_madr_7 : STD_LOGIC; 
  signal N400_MC_D2_PT_12 : STD_LOGIC; 
  signal N400_MC_D2_PT_13 : STD_LOGIC; 
  signal N400_MC_D2 : STD_LOGIC; 
  signal N1334_MC_Q : STD_LOGIC; 
  signal N1334_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1334_MC_D : STD_LOGIC; 
  signal N1334_MC_D1_PT_0 : STD_LOGIC; 
  signal N1334_MC_D1 : STD_LOGIC; 
  signal N1334_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_madr_1_MC_Q : STD_LOGIC; 
  signal uc_ctrl_madr_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_madr_1_MC_D : STD_LOGIC; 
  signal uc_ctrl_madr_1_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_addr_en : STD_LOGIC; 
  signal uc_ctrl_madr_1_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_madr_1_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_madr_1_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_madr_1_MC_D_TFF : STD_LOGIC; 
  signal uc_ctrl_addr_en_MC_Q : STD_LOGIC; 
  signal uc_ctrl_addr_en_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_addr_en_MC_D : STD_LOGIC; 
  signal uc_ctrl_addr_en_MC_D1_PT_0 : STD_LOGIC; 
  signal uc_ctrl_addr_en_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_addr_en_MC_D2 : STD_LOGIC; 
  signal N1335_MC_Q : STD_LOGIC; 
  signal N1335_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1335_MC_D : STD_LOGIC; 
  signal N1335_MC_D1_PT_0 : STD_LOGIC; 
  signal N1335_MC_D1 : STD_LOGIC; 
  signal N1335_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_madr_2_MC_Q : STD_LOGIC; 
  signal uc_ctrl_madr_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_madr_2_MC_D : STD_LOGIC; 
  signal uc_ctrl_madr_2_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_madr_2_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_madr_2_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_madr_2_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_madr_2_MC_D_TFF : STD_LOGIC; 
  signal N1336_MC_Q : STD_LOGIC; 
  signal N1336_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1336_MC_D : STD_LOGIC; 
  signal N1336_MC_D1_PT_0 : STD_LOGIC; 
  signal N1336_MC_D1 : STD_LOGIC; 
  signal N1336_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_madr_3_MC_Q : STD_LOGIC; 
  signal uc_ctrl_madr_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_madr_3_MC_D : STD_LOGIC; 
  signal uc_ctrl_madr_3_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_madr_3_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_madr_3_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_madr_3_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_madr_3_MC_D_TFF : STD_LOGIC; 
  signal N1337_MC_Q : STD_LOGIC; 
  signal N1337_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1337_MC_D : STD_LOGIC; 
  signal N1337_MC_D1_PT_0 : STD_LOGIC; 
  signal N1337_MC_D1 : STD_LOGIC; 
  signal N1337_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_madr_4_MC_Q : STD_LOGIC; 
  signal uc_ctrl_madr_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_madr_4_MC_D : STD_LOGIC; 
  signal uc_ctrl_madr_4_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_madr_4_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_madr_4_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_madr_4_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_madr_4_MC_D_TFF : STD_LOGIC; 
  signal N1338_MC_Q : STD_LOGIC; 
  signal N1338_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1338_MC_D : STD_LOGIC; 
  signal N1338_MC_D1_PT_0 : STD_LOGIC; 
  signal N1338_MC_D1 : STD_LOGIC; 
  signal N1338_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_madr_5_MC_Q : STD_LOGIC; 
  signal uc_ctrl_madr_5_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_madr_5_MC_D : STD_LOGIC; 
  signal uc_ctrl_madr_5_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_madr_5_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_madr_5_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_madr_5_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_madr_5_MC_D_TFF : STD_LOGIC; 
  signal N1339_MC_Q : STD_LOGIC; 
  signal N1339_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1339_MC_D : STD_LOGIC; 
  signal N1339_MC_D1_PT_0 : STD_LOGIC; 
  signal N1339_MC_D1 : STD_LOGIC; 
  signal N1339_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_madr_6_MC_Q : STD_LOGIC; 
  signal uc_ctrl_madr_6_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_madr_6_MC_D : STD_LOGIC; 
  signal uc_ctrl_madr_6_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_madr_6_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_madr_6_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_madr_6_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_madr_6_MC_D_TFF : STD_LOGIC; 
  signal N1340_MC_Q : STD_LOGIC; 
  signal N1340_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1340_MC_D : STD_LOGIC; 
  signal N1340_MC_D1_PT_0 : STD_LOGIC; 
  signal N1340_MC_D1 : STD_LOGIC; 
  signal N1340_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_madr_7_MC_Q : STD_LOGIC; 
  signal uc_ctrl_madr_7_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_madr_7_MC_D : STD_LOGIC; 
  signal uc_ctrl_madr_7_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_madr_7_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_madr_7_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_madr_7_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_madr_7_MC_D_TFF : STD_LOGIC; 
  signal uc_ctrl_prs_state_FFD1_MC_D1 : STD_LOGIC; 
  signal bs_n_II_UIM : STD_LOGIC; 
  signal cs_n_II_UIM : STD_LOGIC; 
  signal uc_ctrl_prs_state_FFD1_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_prs_state_FFD1_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_prs_state_FFD1_MC_D2_PT_2 : STD_LOGIC; 
  signal uc_ctrl_prs_state_FFD1_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_prs_state_FFD1_MC_D_TFF : STD_LOGIC; 
  signal uc_ctrl_stat_en_MC_Q : STD_LOGIC; 
  signal uc_ctrl_stat_en_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_stat_en_MC_D : STD_LOGIC; 
  signal uc_ctrl_stat_en_MC_D1_PT_0 : STD_LOGIC; 
  signal uc_ctrl_stat_en_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_stat_en_MC_D2 : STD_LOGIC; 
  signal mcf_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal mcf_MC_Q : STD_LOGIC; 
  signal mcf_MC_R_OR_PRLD : STD_LOGIC; 
  signal mcf_MC_D : STD_LOGIC; 
  signal mcf_MC_D1_PT_0 : STD_LOGIC; 
  signal mcf_MC_D1 : STD_LOGIC; 
  signal mcf_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_mal_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_mal_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_mal_MC_D : STD_LOGIC; 
  signal smbus_ctrl_mal_MC_CE : STD_LOGIC; 
  signal N1102 : STD_LOGIC; 
  signal smbus_ctrl_mal_MC_CE_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mal_bit_reset : STD_LOGIC; 
  signal smbus_ctrl_mal_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_mal_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_mal_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mal_bit_reset_MC_Q : STD_LOGIC;