smbus_timesim.vhd

可编程器件厂商Xilinx的用于设计SMBus 控制器的源程序

  signal N1533_MC_D2 : STD_LOGIC; 
  signal N1533_MC_D_TFF : STD_LOGIC; 
  signal N1511_MC_Q : STD_LOGIC; 
  signal N1511_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1511_MC_D : STD_LOGIC; 
  signal N1511_MC_D1 : STD_LOGIC; 
  signal N1511_MC_D2_PT_0 : STD_LOGIC; 
  signal N1511_MC_D2_PT_1 : STD_LOGIC; 
  signal N1511_MC_D2 : STD_LOGIC; 
  signal N1511_MC_D_TFF : STD_LOGIC; 
  signal N1531_MC_Q : STD_LOGIC; 
  signal N1531_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1531_MC_D : STD_LOGIC; 
  signal N1531_MC_D1 : STD_LOGIC; 
  signal N1531_MC_D2_PT_0 : STD_LOGIC; 
  signal N1531_MC_D2_PT_1 : STD_LOGIC; 
  signal N1531_MC_D2 : STD_LOGIC; 
  signal N1531_MC_D_TFF : STD_LOGIC; 
  signal N1529_MC_Q : STD_LOGIC; 
  signal N1529_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1529_MC_D : STD_LOGIC; 
  signal N1529_MC_D1 : STD_LOGIC; 
  signal N1529_MC_D2_PT_0 : STD_LOGIC; 
  signal N1529_MC_D2_PT_1 : STD_LOGIC; 
  signal N1529_MC_D2 : STD_LOGIC; 
  signal N1529_MC_D_TFF : STD_LOGIC; 
  signal N568_MC_Q : STD_LOGIC; 
  signal N568_MC_R_OR_PRLD : STD_LOGIC; 
  signal N568_MC_D : STD_LOGIC; 
  signal N568_MC_D1 : STD_LOGIC; 
  signal N568_MC_D2_PT_0 : STD_LOGIC; 
  signal N568_MC_D2_PT_1 : STD_LOGIC; 
  signal N568_MC_D2 : STD_LOGIC; 
  signal N568_MC_D_TFF : STD_LOGIC; 
  signal N565_MC_Q : STD_LOGIC; 
  signal N565_MC_R_OR_PRLD : STD_LOGIC; 
  signal N565_MC_D : STD_LOGIC; 
  signal N565_MC_D1 : STD_LOGIC; 
  signal N565_MC_D2_PT_0 : STD_LOGIC; 
  signal N565_MC_D2_PT_1 : STD_LOGIC; 
  signal N565_MC_D2 : STD_LOGIC; 
  signal N565_MC_D_TFF : STD_LOGIC; 
  signal smbus_ctrl_bus_busy_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_bus_busy_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_bus_busy_MC_D : STD_LOGIC; 
  signal FOOBAR9_ctinst_4 : STD_LOGIC; 
  signal smbus_ctrl_detect_start : STD_LOGIC; 
  signal smbus_ctrl_detect_start_MC_D : STD_LOGIC; 
  signal smbus_ctrl_detect_start_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_detect_start_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_detect_start_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_detect_start_MC_BUFOE_OUT : STD_LOGIC; 
  signal smbus_ctrl_detect_start_MC_OE : STD_LOGIC; 
  signal smbus_ctrl_detect_stop_MC_Q : STD_LOGIC; 
  signal FOOBAR10_ctinst_0 : STD_LOGIC; 
  signal smbus_ctrl_detect_stop_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_detect_stop_MC_D : STD_LOGIC; 
  signal FOOBAR10_ctinst_5 : STD_LOGIC; 
  signal N1116 : STD_LOGIC; 
  signal FOOBAR10_ctinst_4 : STD_LOGIC; 
  signal N1116_MC_Q : STD_LOGIC; 
  signal N1116_MC_D : STD_LOGIC; 
  signal uc_ctrl_mif_bit_reset : STD_LOGIC; 
  signal mcf_MC_UIM : STD_LOGIC; 
  signal smbus_ctrl_mal : STD_LOGIC; 
  signal N1116_MC_D1_PT_0 : STD_LOGIC; 
  signal N1116_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_master_slave : STD_LOGIC; 
  signal N1051 : STD_LOGIC; 
  signal smbus_ctrl_maas : STD_LOGIC; 
  signal N1116_MC_D2_PT_0 : STD_LOGIC; 
  signal N1116_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mif_bit_reset_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mif_bit_reset_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mif_bit_reset_MC_D : STD_LOGIC; 
  signal uc_ctrl_mif_bit_reset_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mif_bit_reset_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_stat_en : STD_LOGIC; 
  signal uc_ctrl_mif_bit_reset_MC_D2_PT_1 : STD_LOGIC; 
  signal data_bus_2_II_UIM : STD_LOGIC; 
  signal uc_ctrl_mif_bit_reset_MC_D2_PT_2 : STD_LOGIC; 
  signal uc_ctrl_mif_bit_reset_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mif_bit_reset_MC_D_TFF : STD_LOGIC; 
  signal rdy_n_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal rdy_n_MC_Q : STD_LOGIC; 
  signal rdy_n_MC_D : STD_LOGIC; 
  signal uc_ctrl_prs_state_FFD1 : STD_LOGIC; 
  signal uc_ctrl_prs_state_FFD2 : STD_LOGIC; 
  signal rdy_n_MC_D1_PT_0 : STD_LOGIC; 
  signal rdy_n_MC_D1 : STD_LOGIC; 
  signal rdy_n_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_prs_state_FFD1_MC_Q : STD_LOGIC; 
  signal FOOBAR8_ctinst_0 : STD_LOGIC; 
  signal uc_ctrl_prs_state_FFD1_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_prs_state_FFD1_MC_D : STD_LOGIC; 
  signal N1080 : STD_LOGIC; 
  signal FOOBAR8_ctinst_4 : STD_LOGIC; 
  signal N1080_MC_Q : STD_LOGIC; 
  signal N1080_MC_D : STD_LOGIC; 
  signal N1080_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mbcr_wr : STD_LOGIC; 
  signal N1080_MC_D2_PT_0 : STD_LOGIC; 
  signal N1080_MC_D2_PT_1 : STD_LOGIC; 
  signal N1080_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbcr_wr_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mbcr_wr_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mbcr_wr_MC_D : STD_LOGIC; 
  signal uc_ctrl_mbcr_wr_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mbcr_wr_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mbcr_wr_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mbcr_wr_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_cntrl_en_MC_Q : STD_LOGIC; 
  signal uc_ctrl_cntrl_en_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_cntrl_en_MC_D : STD_LOGIC; 
  signal addr_bus_0_II_UIM : STD_LOGIC; 
  signal addr_bus_1_II_UIM : STD_LOGIC; 
  signal addr_bus_2_II_UIM : STD_LOGIC; 
  signal addr_bus_3_II_UIM : STD_LOGIC; 
  signal addr_bus_4_II_UIM : STD_LOGIC; 
  signal addr_bus_5_II_UIM : STD_LOGIC; 
  signal addr_bus_6_II_UIM : STD_LOGIC; 
  signal addr_bus_7_II_UIM : STD_LOGIC; 
  signal uc_ctrl_cntrl_en_MC_D1_PT_0 : STD_LOGIC; 
  signal uc_ctrl_cntrl_en_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_cntrl_en_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_prs_state_FFD2_MC_Q : STD_LOGIC; 
  signal uc_ctrl_prs_state_FFD2_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_prs_state_FFD2_MC_D : STD_LOGIC; 
  signal uc_ctrl_prs_state_FFD2_MC_D1 : STD_LOGIC; 
  signal rd_n_II_UIM : STD_LOGIC; 
  signal uc_ctrl_prs_state_FFD2_MC_D2_PT_0 : STD_LOGIC; 
  signal we_n_II_UIM : STD_LOGIC; 
  signal uc_ctrl_prs_state_FFD2_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_prs_state_FFD2_MC_D2 : STD_LOGIC; 
  signal N_PZ_733_MC_Q : STD_LOGIC; 
  signal N_PZ_733_MC_D : STD_LOGIC; 
  signal N_PZ_733_MC_D1_PT_0 : STD_LOGIC; 
  signal N_PZ_733_MC_D1 : STD_LOGIC; 
  signal N_PZ_733_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD2_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_state_FFD2_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_state_FFD2_MC_D : STD_LOGIC; 
  signal FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal FOOBAR2_ctinst_7_tsimcreated_inv_Q : STD_LOGIC; 
  signal FOOBAR2_ctinst_4 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD2_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD2_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD2_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mtx : STD_LOGIC; 
  signal smbus_ctrl_arb_lost : STD_LOGIC; 
  signal N641 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD2_MC_D2_PT_2 : STD_LOGIC; 
  signal N400 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD2_MC_D2_PT_3 : STD_LOGIC; 
  signal N931 : STD_LOGIC; 
  signal N929 : STD_LOGIC; 
  signal N927 : STD_LOGIC; 
  signal N346 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD2_MC_D2_PT_4 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD2_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD2_MC_D_TFF : STD_LOGIC; 
  signal smbus_ctrl_state_FFD1_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_state_FFD1_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_state_FFD1_MC_D : STD_LOGIC; 
  signal smbus_ctrl_state_FFD1_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD1_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD1_MC_D2_PT_1 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD1_MC_D2_PT_2 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD1_MC_D2_PT_3 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD1_MC_D2_PT_4 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD1_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD3_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_state_FFD3_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_state_FFD3_MC_D : STD_LOGIC; 
  signal smbus_ctrl_state_FFD3_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD3_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD3_MC_D2_PT_1 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD3_MC_D2_PT_2 : STD_LOGIC; 
  signal N_PZ_806 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD3_MC_D2_PT_3 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD3_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD3_MC_D_TFF : STD_LOGIC; 
  signal N641_MC_Q : STD_LOGIC; 
  signal N641_MC_D : STD_LOGIC; 
  signal N641_MC_D1 : STD_LOGIC; 
  signal N641_MC_D2_PT_0 : STD_LOGIC; 
  signal N641_MC_D2_PT_1 : STD_LOGIC; 
  signal N641_MC_D2 : STD_LOGIC; 
  signal N931_MC_Q : STD_LOGIC; 
  signal N931_MC_R_OR_PRLD : STD_LOGIC; 
  signal N931_MC_D : STD_LOGIC; 
  signal N931_MC_D1 : STD_LOGIC; 
  signal N931_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_726 : STD_LOGIC; 
  signal N931_MC_D2_PT_1 : STD_LOGIC; 
  signal N931_MC_D2 : STD_LOGIC; 
  signal N931_MC_D_TFF : STD_LOGIC; 
  signal N_PZ_806_MC_Q : STD_LOGIC; 
  signal N_PZ_806_MC_D : STD_LOGIC; 
  signal N_PZ_806_MC_D1 : STD_LOGIC; 
  signal N_PZ_806_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_806_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_806_MC_D2 : STD_LOGIC; 
  signal N_PZ_726_MC_Q : STD_LOGIC; 
  signal N_PZ_726_MC_D : STD_LOGIC; 
  signal N_PZ_726_MC_D1 : STD_LOGIC; 
  signal N_PZ_726_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_726_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_726_MC_D2_PT_2 : STD_LOGIC; 
  signal N_PZ_726_MC_D2 : STD_LOGIC; 
  signal N929_MC_Q : STD_LOGIC; 
  signal N929_MC_R_OR_PRLD : STD_LOGIC; 
  signal N929_MC_D : STD_LOGIC; 
  signal N929_MC_D1 : STD_LOGIC; 
  signal N929_MC_D2_PT_0 : STD_LOGIC; 
  signal N929_MC_D2_PT_1 : STD_LOGIC; 
  signal N929_MC_D2 : STD_LOGIC; 
  signal N929_MC_D_TFF : STD_LOGIC; 
  signal N927_MC_Q : STD_LOGIC; 
  signal N927_MC_R_OR_PRLD : STD_LOGIC; 
  signal N927_MC_D : STD_LOGIC; 
  signal N927_MC_D1 : STD_LOGIC; 
  signal N927_MC_D2_PT_0 : STD_LOGIC; 
  signal N927_MC_D2_PT_1 : STD_LOGIC; 
  signal N927_MC_D2 : STD_LOGIC; 
  signal N927_MC_D_TFF : STD_LOGIC; 
  signal N346_MC_Q : STD_LOGIC; 
  signal N346_MC_R_OR_PRLD : STD_LOGIC; 
  signal N346_MC_D : STD_LOGIC; 
  signal N346_MC_D1 : STD_LOGIC; 
  signal N346_MC_D2_PT_0 : STD_LOGIC; 
  signal N346_MC_D2_PT_1 : STD_LOGIC; 
  signal N346_MC_D2 : STD_LOGIC; 
  signal N346_MC_D_TFF : STD_LOGIC; 
  signal smbus_ctrl_arb_lost_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_arb_lost_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_arb_lost_MC_D : STD_LOGIC; 
  signal smbus_ctrl_arb_lost_MC_D1 : STD_LOGIC; 
  signal N1065 : STD_LOGIC; 
  signal smbus_ctrl_arb_lost_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_sda_out_reg_d1 : STD_LOGIC; 
  signal smbus_ctrl_arb_lost_MC_D2_PT_1 : STD_LOGIC; 
  signal smbus_ctrl_arb_lost_MC_D2_PT_2 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT1 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT3 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT2 : STD_LOGIC; 
  signal smbus_ctrl_arb_lost_MC_D2_PT_3 : STD_LOGIC; 
  signal smbus_ctrl_arb_lost_MC_D2 : STD_LOGIC; 
  signal N1065_MC_Q : STD_LOGIC; 
  signal N1065_MC_D : STD_LOGIC; 
  signal N1065_MC_D1 : STD_LOGIC; 
  signal N_PZ_653 : STD_LOGIC; 
  signal N1065_MC_D2_PT_0 : STD_LOGIC; 
  signal N1065_MC_D2_PT_1 : STD_LOGIC; 
  signal N1065_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT2_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT2_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT2_MC_D : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT2_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT2_MC_D1 : STD_LOGIC; 
  signal N571 : STD_LOGIC; 
  signal N583 : STD_LOGIC; 
  signal N580 : STD_LOGIC; 
  signal N751 : STD_LOGIC; 
  signal N749 : STD_LOGIC; 
  signal N589 : STD_LOGIC; 
  signal N586 : STD_LOGIC; 
  signal N577 : STD_LOGIC; 
  signal N_PZ_657 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT2_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_734 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT2_MC_D2_PT_1 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT2_MC_D2_PT_2 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT2_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT3_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT3_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT3_MC_D : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT3_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT3_MC_D1 : STD_LOGIC; 
  signal N574 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT3_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT3_MC_D2_PT_1 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT3_MC_D2_PT_2 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT3_MC_D2_PT_3 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT3_MC_D2_PT_4 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT3_MC_D2_PT_5 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT3_MC_D2_PT_6 : STD_LOGIC; 
  signal smbus_ctrl_rep_start_det_reg : STD_LOGIC; 
  signal uc_ctrl_rsta : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT3_MC_D2_PT_7 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT3_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT1_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT1_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT1_MC_D : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT1_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT1_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT1_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT1_MC_D2_PT_1 : STD_LOGIC; 
  signal smbus_ctrl_gen_start : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT1_MC_D2_PT_2 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT1_MC_D2_PT_3 : STD_LOGIC; 
  signal smbus_ctrl_scl_state_FFT1_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_master_slave_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_master_slave_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_master_slave_MC_D : STD_LOGIC;