smbus_timesim.vhd

可编程器件厂商Xilinx的用于设计SMBus 控制器的源程序

-- Xilinx Vhdl produced by program ngd2vhdl E.35
-- Command: -rpw 100 -tpw 1 -ar Structure -xon true -w smbus.nga smbus_timesim.vhd 
-- Input file: smbus.nga
-- Output file: smbus_timesim.vhd
-- Design name: smbus
-- Xilinx: C:/xilinx_webpack_42wp00_rc2
-- # of Entities: 1
-- Device: XCR3256XL-7-TQ144

-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized,
-- or used in any other manner other than simulation. This netlist uses simulation
-- primitives which may not represent the true implementation of the device, however
-- the netlist is functionally correct. Do not modify this file.

-- Model for  ROC (Reset-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity ROC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 100 ns);
  port(O : out std_ulogic := '1') ;
  attribute VITAL_LEVEL0 of ROC : entity is TRUE;
end ROC;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    if (WIDTH <= 0 ns) then
       assert FALSE report
       "*** Error: a positive value of WIDTH must be specified ***"
       severity failure;
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end ROC_V;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity smbus is
  port (
    bs_n : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    cs_n : in STD_LOGIC := 'X'; 
    rd_wrn : in STD_LOGIC := 'X'; 
    sda : inout STD_LOGIC; 
    scl : inout STD_LOGIC; 
    we_n : in STD_LOGIC := 'X'; 
    rd_n : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    irq : out STD_LOGIC; 
    mcf : out STD_LOGIC; 
    rdy_n : out STD_LOGIC; 
    addr_bus : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    data_bus : inout STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end smbus;

architecture Structure of smbus is
  component ROC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 100 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  signal data_bus_0_MC_Q : STD_LOGIC; 
  signal data_bus_0_MC_OE : STD_LOGIC; 
  signal data_bus_0_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal FOOBAR1_ctinst_2 : STD_LOGIC; 
  signal data_bus_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_bus_0_MC_D : STD_LOGIC; 
  signal clk_II_FCLK : STD_LOGIC; 
  signal smbus_ctrl_scl_out_reg : STD_LOGIC; 
  signal FOOBAR1_ctinst_0 : STD_LOGIC; 
  signal N1323 : STD_LOGIC; 
  signal FOOBAR1_ctinst_1 : STD_LOGIC; 
  signal reset_II_UIM : STD_LOGIC; 
  signal N913 : STD_LOGIC; 
  signal FOOBAR1_ctinst_3 : STD_LOGIC; 
  signal sda_II_UIM : STD_LOGIC; 
  signal FOOBAR1_ctinst_4 : STD_LOGIC; 
  signal smbus_ctrl_scl_out_reg_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_scl_out_reg_MC_D : STD_LOGIC; 
  signal FOOBAR4_ctinst_7 : STD_LOGIC; 
  signal uc_ctrl_men : STD_LOGIC; 
  signal smbus_ctrl_detect_stop : STD_LOGIC; 
  signal FOOBAR4_ctinst_0 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD2 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD3 : STD_LOGIC; 
  signal smbus_ctrl_state_FFD1 : STD_LOGIC; 
  signal FOOBAR4_ctinst_4 : STD_LOGIC; 
  signal uc_ctrl_men_MC_Q : STD_LOGIC; 
  signal FOOBAR5_ctinst_0 : STD_LOGIC; 
  signal uc_ctrl_men_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_men_MC_D : STD_LOGIC; 
  signal uc_ctrl_men_MC_D1_PT_0 : STD_LOGIC; 
  signal uc_ctrl_men_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_watchdog_state_FFD1 : STD_LOGIC; 
  signal smbus_ctrl_watchdog_state_FFD2 : STD_LOGIC; 
  signal uc_ctrl_men_MC_D2_PT_0 : STD_LOGIC; 
  signal rd_wrn_II_UIM : STD_LOGIC; 
  signal rdy_n_MC_UIM : STD_LOGIC; 
  signal uc_ctrl_cntrl_en : STD_LOGIC; 
  signal N_PZ_733 : STD_LOGIC; 
  signal data_bus_7_II_UIM : STD_LOGIC; 
  signal uc_ctrl_men_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_men_MC_D2_PT_2 : STD_LOGIC; 
  signal uc_ctrl_men_MC_D2_PT_3 : STD_LOGIC; 
  signal uc_ctrl_men_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_watchdog_state_FFD1_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_watchdog_state_FFD1_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_watchdog_state_FFD1_MC_D : STD_LOGIC; 
  signal smbus_ctrl_watchdog_state_FFD1_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_scl_in : STD_LOGIC; 
  signal smbus_ctrl_watchdog_state_FFD1_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_watchdog_state_FFD1_MC_D2_PT_1 : STD_LOGIC; 
  signal N1547 : STD_LOGIC; 
  signal N556 : STD_LOGIC; 
  signal N559 : STD_LOGIC; 
  signal N562 : STD_LOGIC; 
  signal N1544 : STD_LOGIC; 
  signal N1523 : STD_LOGIC; 
  signal N1521 : STD_LOGIC; 
  signal N1542 : STD_LOGIC; 
  signal N553 : STD_LOGIC; 
  signal N1519 : STD_LOGIC; 
  signal N550 : STD_LOGIC; 
  signal N547 : STD_LOGIC; 
  signal N1539 : STD_LOGIC; 
  signal N1515 : STD_LOGIC; 
  signal N1513 : STD_LOGIC; 
  signal N1533 : STD_LOGIC; 
  signal N1511 : STD_LOGIC; 
  signal N1531 : STD_LOGIC; 
  signal N1529 : STD_LOGIC; 
  signal N568 : STD_LOGIC; 
  signal N565 : STD_LOGIC; 
  signal smbus_ctrl_watchdog_state_FFD1_MC_D2_PT_2 : STD_LOGIC; 
  signal smbus_ctrl_bus_busy : STD_LOGIC; 
  signal smbus_ctrl_watchdog_state_FFD1_MC_D2_PT_3 : STD_LOGIC; 
  signal smbus_ctrl_watchdog_state_FFD1_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_scl_in_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_scl_in_MC_D : STD_LOGIC; 
  signal scl_II_UIM : STD_LOGIC; 
  signal smbus_ctrl_scl_in_MC_D1_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_scl_in_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_scl_in_MC_D2 : STD_LOGIC; 
  signal FOOBAR1_ctinst_4_tsimcreated_inv_Q : STD_LOGIC; 
  signal smbus_ctrl_detect_start_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal smbus_ctrl_watchdog_state_FFD2_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_watchdog_state_FFD2_MC_R_OR_PRLD : STD_LOGIC; 
  signal smbus_ctrl_watchdog_state_FFD2_MC_D : STD_LOGIC; 
  signal smbus_ctrl_watchdog_state_FFD2_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_sda_in : STD_LOGIC; 
  signal smbus_ctrl_watchdog_state_FFD2_MC_D2_PT_0 : STD_LOGIC; 
  signal smbus_ctrl_watchdog_state_FFD2_MC_D2_PT_1 : STD_LOGIC; 
  signal smbus_ctrl_watchdog_state_FFD2_MC_D2_PT_2 : STD_LOGIC; 
  signal smbus_ctrl_watchdog_state_FFD2_MC_D2_PT_3 : STD_LOGIC; 
  signal smbus_ctrl_watchdog_state_FFD2_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_sda_in_MC_D : STD_LOGIC; 
  signal smbus_ctrl_sda_in_MC_Q : STD_LOGIC; 
  signal smbus_ctrl_sda_in_MC_D1 : STD_LOGIC; 
  signal smbus_ctrl_sda_in_MC_D2 : STD_LOGIC; 
  signal smbus_ctrl_sda_in_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal smbus_ctrl_sda_in_MC_BUFOE_OUT : STD_LOGIC; 
  signal smbus_ctrl_sda_in_MC_OE : STD_LOGIC; 
  signal N1547_MC_Q : STD_LOGIC; 
  signal N1547_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1547_MC_D : STD_LOGIC; 
  signal N_PZ_607 : STD_LOGIC; 
  signal N1547_MC_D1_PT_0 : STD_LOGIC; 
  signal N1547_MC_D1 : STD_LOGIC; 
  signal N1547_MC_D2 : STD_LOGIC; 
  signal N_PZ_607_MC_Q : STD_LOGIC; 
  signal N_PZ_607_MC_D : STD_LOGIC; 
  signal N_PZ_607_MC_D1 : STD_LOGIC; 
  signal N_PZ_607_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_607_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_607_MC_D2_PT_2 : STD_LOGIC; 
  signal N_PZ_607_MC_D2 : STD_LOGIC; 
  signal N556_MC_Q : STD_LOGIC; 
  signal N556_MC_R_OR_PRLD : STD_LOGIC; 
  signal N556_MC_D : STD_LOGIC; 
  signal N556_MC_D1 : STD_LOGIC; 
  signal N556_MC_D2_PT_0 : STD_LOGIC; 
  signal N556_MC_D2_PT_1 : STD_LOGIC; 
  signal N556_MC_D2 : STD_LOGIC; 
  signal N556_MC_D_TFF : STD_LOGIC; 
  signal N559_MC_Q : STD_LOGIC; 
  signal N559_MC_R_OR_PRLD : STD_LOGIC; 
  signal N559_MC_D : STD_LOGIC; 
  signal N559_MC_D1 : STD_LOGIC; 
  signal N559_MC_D2_PT_0 : STD_LOGIC; 
  signal N559_MC_D2_PT_1 : STD_LOGIC; 
  signal N559_MC_D2 : STD_LOGIC; 
  signal N559_MC_D_TFF : STD_LOGIC; 
  signal N562_MC_Q : STD_LOGIC; 
  signal N562_MC_R_OR_PRLD : STD_LOGIC; 
  signal N562_MC_D : STD_LOGIC; 
  signal N562_MC_D1 : STD_LOGIC; 
  signal N562_MC_D2_PT_0 : STD_LOGIC; 
  signal N562_MC_D2_PT_1 : STD_LOGIC; 
  signal N562_MC_D2 : STD_LOGIC; 
  signal N562_MC_D_TFF : STD_LOGIC; 
  signal N1544_MC_Q : STD_LOGIC; 
  signal N1544_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1544_MC_D : STD_LOGIC; 
  signal N1544_MC_D1 : STD_LOGIC; 
  signal N1544_MC_D2_PT_0 : STD_LOGIC; 
  signal N1544_MC_D2_PT_1 : STD_LOGIC; 
  signal N1544_MC_D2 : STD_LOGIC; 
  signal N1544_MC_D_TFF : STD_LOGIC; 
  signal N1523_MC_Q : STD_LOGIC; 
  signal N1523_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1523_MC_D : STD_LOGIC; 
  signal N1523_MC_D1 : STD_LOGIC; 
  signal N1523_MC_D2_PT_0 : STD_LOGIC; 
  signal N1523_MC_D2_PT_1 : STD_LOGIC; 
  signal N1523_MC_D2 : STD_LOGIC; 
  signal N1523_MC_D_TFF : STD_LOGIC; 
  signal N1521_MC_Q : STD_LOGIC; 
  signal N1521_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1521_MC_D : STD_LOGIC; 
  signal N1521_MC_D1 : STD_LOGIC; 
  signal N1521_MC_D2_PT_0 : STD_LOGIC; 
  signal N1521_MC_D2_PT_1 : STD_LOGIC; 
  signal N1521_MC_D2 : STD_LOGIC; 
  signal N1521_MC_D_TFF : STD_LOGIC; 
  signal N1542_MC_Q : STD_LOGIC; 
  signal N1542_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1542_MC_D : STD_LOGIC; 
  signal N1542_MC_D1 : STD_LOGIC; 
  signal N1542_MC_D2_PT_0 : STD_LOGIC; 
  signal N1542_MC_D2_PT_1 : STD_LOGIC; 
  signal N1542_MC_D2 : STD_LOGIC; 
  signal N1542_MC_D_TFF : STD_LOGIC; 
  signal N553_MC_Q : STD_LOGIC; 
  signal N553_MC_R_OR_PRLD : STD_LOGIC; 
  signal N553_MC_D : STD_LOGIC; 
  signal N553_MC_D1 : STD_LOGIC; 
  signal N553_MC_D2_PT_0 : STD_LOGIC; 
  signal N553_MC_D2_PT_1 : STD_LOGIC; 
  signal N553_MC_D2 : STD_LOGIC; 
  signal N553_MC_D_TFF : STD_LOGIC; 
  signal N1519_MC_Q : STD_LOGIC; 
  signal N1519_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1519_MC_D : STD_LOGIC; 
  signal N1519_MC_D1 : STD_LOGIC; 
  signal N1519_MC_D2_PT_0 : STD_LOGIC; 
  signal N1519_MC_D2_PT_1 : STD_LOGIC; 
  signal N1519_MC_D2 : STD_LOGIC; 
  signal N1519_MC_D_TFF : STD_LOGIC; 
  signal N550_MC_Q : STD_LOGIC; 
  signal N550_MC_R_OR_PRLD : STD_LOGIC; 
  signal N550_MC_D : STD_LOGIC; 
  signal N550_MC_D1 : STD_LOGIC; 
  signal N550_MC_D2_PT_0 : STD_LOGIC; 
  signal N550_MC_D2_PT_1 : STD_LOGIC; 
  signal N550_MC_D2 : STD_LOGIC; 
  signal N550_MC_D_TFF : STD_LOGIC; 
  signal N547_MC_Q : STD_LOGIC; 
  signal N547_MC_R_OR_PRLD : STD_LOGIC; 
  signal N547_MC_D : STD_LOGIC; 
  signal N547_MC_D1 : STD_LOGIC; 
  signal N547_MC_D2_PT_0 : STD_LOGIC; 
  signal N547_MC_D2_PT_1 : STD_LOGIC; 
  signal N547_MC_D2 : STD_LOGIC; 
  signal N547_MC_D_TFF : STD_LOGIC; 
  signal N1539_MC_Q : STD_LOGIC; 
  signal N1539_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1539_MC_D : STD_LOGIC; 
  signal N1539_MC_D1 : STD_LOGIC; 
  signal N1539_MC_D2_PT_0 : STD_LOGIC; 
  signal N1539_MC_D2_PT_1 : STD_LOGIC; 
  signal N1539_MC_D2 : STD_LOGIC; 
  signal N1539_MC_D_TFF : STD_LOGIC; 
  signal N1515_MC_Q : STD_LOGIC; 
  signal N1515_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1515_MC_D : STD_LOGIC; 
  signal N1515_MC_D1 : STD_LOGIC; 
  signal N1515_MC_D2_PT_0 : STD_LOGIC; 
  signal N1515_MC_D2_PT_1 : STD_LOGIC; 
  signal N1515_MC_D2 : STD_LOGIC; 
  signal N1515_MC_D_TFF : STD_LOGIC; 
  signal N1513_MC_Q : STD_LOGIC; 
  signal N1513_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1513_MC_D : STD_LOGIC; 
  signal N1513_MC_D1 : STD_LOGIC; 
  signal N1513_MC_D2_PT_0 : STD_LOGIC; 
  signal N1513_MC_D2_PT_1 : STD_LOGIC; 
  signal N1513_MC_D2 : STD_LOGIC; 
  signal N1513_MC_D_TFF : STD_LOGIC; 
  signal N1533_MC_Q : STD_LOGIC; 
  signal N1533_MC_R_OR_PRLD : STD_LOGIC; 
  signal N1533_MC_D : STD_LOGIC; 
  signal N1533_MC_D1 : STD_LOGIC; 
  signal N1533_MC_D2_PT_0 : STD_LOGIC; 
  signal N1533_MC_D2_PT_1 : STD_LOGIC;