8倍频vhdl.txt

该文件可用vhdl语言实现时钟8倍频

library ieee;
use ieee.std_logic_1164.all;
--library unisim;
--use unisim.vcomponents.all;
entity dll_8x is
port (
clkin : in std_logic;
reset : in std_logic;
clk2x : out std_logic;
clk4x : out std_logic;
clk8x : out std_logic;
locked: out std_logic
);
end dll_8x;
architecture a of dll_8x is
component ibufg

port (
i : in std_logic; 
o : out std_logic
);
end component;

component ibuf
port (
i : in std_logic; 
o : out std_logic
);
end component;

component clkdll
port (
clkin,clkfb,rst: in std_logic;
clk0,clk90,clk180,clk270,clk2x,clkdv,locked: out std_logic
);
end component;


component bufg
port (
i : in std_logic; 
o : out std_logic
);
end component;

component obuf
port (
i : in std_logic; 
o : out std_logic
);
end component;

component srl16
port (
d : in std_logic; 
clk : in std_logic; 
a0 : in std_logic; 
a1 : in std_logic; 
a2 : in std_logic; 
a3 : in std_logic; 
q : out std_logic
); 
end component;

signal clkin_w,reset_w,clk2x_dll,clk2x_g,clk4x_dll,clk4x_g,clk8x_dll,clk8x_g : std_logic;
signal locked2x,locked2x_delay,reset4x,locked4x_dll : std_logic;
signal locked4x,locked4x_delay,reset8x,locked8x_dll : std_logic;
signal logic1 : std_logic;

begin 
logic1 <= '1';
clkpad : ibufg port map (
i=>clkin, 
o=>clkin_w
);



rstpad : ibuf port map (
i=>reset, 
o=>reset_w
);

dll2x : clkdll port map (
clkin=>clkin_w, 
clkfb=>clk2x_g, 
rst=>reset_w,
clk0=>open, 
clk90=>open, 
clk180=>open, 
clk270=>open,
clk2x=>clk2x_dll, 
clkdv=>open, 
locked=>locked2x
);
clk2xg : bufg port map (
i=>clk2x_dll, 
o=>clk2x_g
);
rstsrl : SRL16 port map (
d=>locked2x, 
clk=>clk2x_g, 
q=>locked2x_delay,
a3=>logic1, 
a2=>logic1, 
a1=>logic1, 
a0=>logic1
);
reset4x <= not locked2x_delay;
dll4x : clkdll port map (
clkin=>clk2x_g, 
clkfb=>clk4x_g, 
rst=>reset4x,
clk0=>open, 
clk90=>open, 
clk180=>open, 
clk270=>open,
clk2x=>clk4x_dll, 
clkdv=>open, 
locked=>locked4x
);

clk4xg : bufg port map (
i=>clk4x_dll,
o=>clk4x_g 
);

rstsr2 : SRL16 port map (
d=>locked4x, 
clk=>clk4x_g, 
q=>locked4x_delay,
a3=>logic1, 
a2=>logic1, 
a1=>logic1, 
a0=>logic1
);
reset8x <= not locked4x_delay;

dll8x : clkdll port map (
clkin=>clk4x_g, 
clkfb=>clk8x_g, 
rst=>reset8x,
clk0=>open, 
clk90=>open, 
clk180=>open, 
clk270=>open,
clk2x=>clk8x_dll, 
clkdv=>open, 
locked=>locked8x_dll
);

clk8xg : bufg port map (
i=>clk8x_dll,
o=>clk8x_g 
);

lckpad : obuf port map (
i=>locked8x_dll, 
o=>locked
);

clk2x <= clk2x_g;
clk4x <= clk4x_g;
clk8x <= clk8x_g;

end a;