📄 kinvert.vhd
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-- description for inverter
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY kinvert IS
PORT (A : IN std_logic;
B : OUT std_logic);
END kinvert;
ARCHITECTURE kinvert_arc OF kinvert IS
BEGIN
B <= NOT A;
END kinvert_arc;
-- end of description for inverter
-- description for inverter with enable
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY ken1 IS
PORT (A,B : IN std_logic;
C : OUT std_logic);
END ken1;
ARCHITECTURE ken1_arc OF ken1 IS
BEGIN
PROCESS(A,B)
BEGIN
IF (B = '1') THEN
C <= NOT A;
ELSE
C <= '1';
END IF;
END PROCESS;
END ken1_arc;
-- end of description for inverter with enable
-- description for buffer
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY direct IS
PORT (A : IN std_logic;
B : OUT std_logic);
END direct;
ARCHITECTURE direct_arc OF direct IS
BEGIN
B <= A;
END direct_arc;
-- end of description for buffer
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