📄 kf_f.vhd
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LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY kf_f IS
PORT (A,B : IN std_logic;
C : OUT std_logic);
END kf_f;
ARCHITECTURE kf_f_arc OF kf_f IS
COMPONENT knand2
PORT (A,B : IN std_logic;
C : OUT std_logic);
END COMPONENT;
SIGNAL tmp1,tmp2 : std_logic;
BEGIN
U0: knand2 PORT MAP(A,tmp1,tmp2);
U1: knand2 PORT MAP(tmp2,B,tmp1);
C <= tmp2;
END kf_f_arc;
-- two inputs and_not gate description
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY knand2 IS
PORT (A,B : IN std_logic;
C : OUT std_logic);
END knand2;
ARCHITECTURE knand2_arc OF knand2 IS
BEGIN
C <= NOT (A AND B);
END knand2_arc;
-- end of two inputs and_not gate description
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