ksy.vhd

里面有一个很实用的源码,数字引爆密码设计

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY ksy IS
           PORT (A,B  : IN  std_logic;
                 C    : OUT  std_logic);
END ksy;

ARCHITECTURE ksy_arc OF ksy IS
     COMPONENT kand2
          PORT (A,B  : IN  std_logic;
                C    : OUT std_logic);
     END COMPONENT;

     COMPONENT kdf
          PORT (A,B  : IN  std_logic;
                C,D  : OUT std_logic);
     END COMPONENT;

     COMPONENT knand2
          PORT (A,B  : IN  std_logic;
                C    : OUT std_logic);
     END COMPONENT;
     SIGNAL  TMP1,TMP2,TMP3,TMP4,TMP5,TMP6  : std_logic;
BEGIN
     U0: knand2   PORT MAP(A,TMP1,TMP2);
     U1: knand2   PORT MAP(TMP2,TMP3,TMP1);
     U2: kdf      PORT MAP(TMP2,B,TMP4,TMP3);
     U3: kdf      PORT MAP(TMP4,B,TMP6,TMP5);  
     U4: kand2    PORT MAP(TMP4,TMP5,C);
END ksy_arc;

-- two inputs and gate description
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY kand2 IS
           PORT (A,B  : IN  std_logic;
                 C    : OUT  std_logic);
END KAND2;

ARCHITECTURE kand2_arc OF kand2 IS
BEGIN
     C <= A AND B;
END kand2_arc;
-- end of two inputs and gate description

-- two inputs and_not gate description
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY knand2 IS
           PORT (A,B  : IN  std_logic;
                 C    : OUT  std_logic);
END knand2;

ARCHITECTURE knand2_arc OF knand2 IS
BEGIN
     C <= NOT (A AND B);
END knand2_arc;
-- end of two inputs and_not gate description

-- D trigger description
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY kdf IS
           PORT (A,B  : IN  std_logic;
                 C,D  : OUT  std_logic);
END kdf;

ARCHITECTURE kdf_arc OF kdf IS
BEGIN
     PROCESS(B)
     BEGIN
          IF ( B'event AND B ='1') THEN
               C <= A;
	       D <= NOT A;
          END IF;
     END PROCESS;
END kdf_arc;
-- end of D trigger description