qiangdaqi.vhd

扳动定义为“开始”（即enable）的开关后

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity qiangdaqi is
port(enable:in std_logic;
     --reset:in std_logic;
	  a:in std_logic;
	  b:in std_logic;
	  c:in std_logic;
	  d:in std_logic;
	  clk:in std_logic;
	  spkout:out std_logic;
	  cs:buffer std_logic_vector(1 downto 0);
	  --cs:buffer std_logic;
	  led:out std_logic_vector(7 downto 0);
	  seg:out std_logic_vector(3 downto 0);
	  segment:out std_logic_vector(7 downto 0)
	  );
end qiangdaqi;

architecture Behavioral of qiangdaqi is
-- signal led1,led0:std_logic_vector(7 downto 0);
signal flag:std_logic;
signal output:std_logic_vector(3 downto 0);
signal start:std_logic;
signal index:std_logic_vector(5 downto 0);
signal count: std_logic_vector(25 downto 0);
signal fclk:std_logic;
--signal led1:std_logic_vector(7 downto 0);

component input is
    port(--en:in std_logic;
	      clk:in std_logic;
			--reset:in std_logic;
	      a:in std_logic;
			b:in std_logic;
			c:in std_logic;
			d:in std_logic;
			output:out std_logic_vector(3 downto 0);
			flag:out std_logic);
end component;

component light is
    port(--en:in std_logic;
	      clk:std_logic;
			input:in std_logic_vector(3 downto 0);
			flag:in std_logic;
			seg:out std_logic_vector(3 downto 0);
			ledout:out std_logic_vector(7 downto 0));
end component;

component control is
    port(start:in std_logic;
	      a:in std_logic;
			b:in std_logic;
			c:in std_logic;
			d:in std_logic;
			clk:in std_logic;
			spkout:out std_logic;
			index:buffer std_logic_vector(5 downto 0)
         );
end component;

--component lcd is
   -- port(clk:in std_logic;
		--	enable:in std_logic;
		--	led:out std_logic_vector(7 downto 0);
		--	cs:buffer std_logic_vector(1 downto 0);
		--	start:out std_logic
--			);
--end component;

begin
--cs<=cs1;
--led<=led1;
process(fclk,enable)
begin
--cs<="00";
--led<="11111111";
     if fclk'event and  fclk='1' then
        if  enable='0' then
		      cs<="01";
				--led<="11111111";
				if(fclk='1') then
	         led<="11111110";
				end if;
				if(fclk='0') then
	         led<="11111100";
				end if;
				if(fclk='1') then
	         led<="11111000";
				end if;
				if(fclk='0') then
	         led<="11110000";
				end if;
				if(fclk='1') then
	         led<="11100000";
				end if;
				if(fclk='0') then
	         led<="11000000";
				end if;
				if(fclk='1') then
	         led<="10000000";
				end if;
				if(fclk='0') then
	         led<="00000000";
				end if;
	         start <='1';
			else
            start<='0';
				cs<="00";
		      --led<="11111111";
			end if;
	  end if;
end process;

process(clk)
begin
 	if (clk'event and clk='1') then
	  if(count=50000000)	then
	    count<="00000000000000000000000000";
	  else
		 count<=count+1;
     end if;
	end if;
end process;

fclk <= count(25);

--process(fclk)
--begin
--if(fclk'event and fclk='1') then
   --counter<="000";



--process(clk,enable)
--begin
--if(clk'event and clk='1') then
  -- if(enable'event and enable='0') then
     --   cs<="01";
	  --   led<="11111110";
	  --   led<="11111100";
	  --   led<="11111000";
	  --   led<="11110000";
	  --   led<="11100000";
	  --   led<="11000000";
	  --   led<="10000000";
	  --   led<="00000000";
	  --   start <='1';
--	else
	   --  led<="11111111";
		--  start<='0';
--	end if;
--end if;
--end process;

u1:input port map(clk,a,b,c,d,output,flag);
u2:light port map(clk,output,flag,seg,segment);
u3:control port map(start,a,b,c,d,clk,spkout,index);
--u4:lcd port map(fclk,enable,led1,cs1,start);

end Behavioral;