bi_plus_occure_and_scale.v

Verilog HDL 程序 双路脉冲发生器的代码 包含了键盘控制

/*************************module plus_occure*****************************/
//it should set as 100M = 100000000
`define clk_freq   32'd300

module plus_occure(write_data_enable,freq_data,dead_data,clk,plus_1,plus_2);
input [15:0] freq_data,dead_data;
input clk,write_data_enable;
output plus_1,plus_2;

reg plus_1,plus_2;

reg [15:0] static_count_data,static_dead_data;

always@(posedge clk)
if(write_data_enable)
begin
	countdata = freq_data;
	static_dead_data = dead_data;
end
//change freq  to count data
reg [15:0]countdata;
always@(countdata)
begin
	static_count_data = ( countdata/2 + `clk_freq )/countdata;
end

reg status_ctler;

sta_ctl  stactl(.dead_data(static_dead_data),.freq_data(static_count_data),.clock(clk),.status_ctl(status_ctler));

status sta(.sta_ctl(status_ctler),.plus1(plus_1),.plus2(plus_2));


endmodule


module sta_ctl(dead_data,freq_data,clock,status_ctl);
input [15:0]dead_data,freq_data;
input clock;
output status_ctl;

reg status_ctl;
reg [15:0]count_data;

always@(posedge clock)
begin
	if(count_data == 16'b1111111111111111)
		count_data = 16'd0;
	else if(count_data!=0)
		count_data = count_data - 16'd1;
	
	
	if(count_data==0)
		begin
		count_data = freq_data;
		status_ctl = 1'b0;
		end
	else if(count_data == dead_data+1)
		begin
		//count_data = count_data-16'd1;
		status_ctl = 1'b1;
		end
	else if(count_data == dead_data)
		begin
		//count_data = count_data-16'd1;
		status_ctl = 1'b0;
		end
	else if(count_data == 16'd1)
		begin
		//count_data = count_data-16'd1;
		status_ctl = 1'b1;
		end
end

endmodule

module status(sta_ctl,plus1,plus2);
input sta_ctl;
output plus1,plus2;
reg plus1= 1'b0;
reg plus2= 1'b1;

parameter 	s_lh=2'b00,
			s_dt1=2'b01,
			s_hl=2'b10,
			s_dt2=2'b11;
			
reg [1:0] sta;


always @(sta)
	case(sta)
	s_lh:	begin
			plus1 = 1'b0;
			plus2 = 1'b1;
			end
	s_dt1:	begin
			plus1=1'b0;
			plus2=1'b0;
			end
	s_hl:	begin
			plus1=1'b1;
			plus2=1'b0;
			end
	s_dt2:	begin
			plus1=1'b0;
			plus2=1'b0;
			end
	default: begin
			plus1 = 1'b0;
			plus2 = 1'b1;
			end
	endcase

always @(posedge sta_ctl)
	case(sta)
		s_lh:	sta = s_dt1;
		s_dt1:	sta = s_hl;
		s_hl:	sta = s_dt2;
		s_dt2:	sta = s_lh;
		default:sta = s_lh;
	endcase

endmodule


/*******************************module freq_scale****************************/
//it should set as hight as possable.
//for that wo can get the freq ever >0.1s it should set as 0.1s / (1/15k)= 1500
/*
`define max_plus_num 5


module freq_scale(enable,plus_in,clk,freq_data);
input clk,plus_in,enable;
output [15:0]freq_data;
reg [15:0]freq_data;


reg [15:0]plus_count;
reg [15:0]clk_count;
//reg count_flag;
//reg [15:0]scale_cycle_flag;

always@(posedge plus_in) //ji shu plus_count  
begin		
	if(enable)
	begin
		if(plus_count != 0)
			plus_count = plus_count -16'd1;
		else
			begin
			plus_count =`max_plus_num;
			end
		if(plus_count == 0)
			freq_data = (`max_plus_num - 16'd1) * `clk_freq / clk_count;
	end
end	

always@(posedge clk)
begin
	if(plus_count == `max_plus_num)
		begin
		clk_count = 16'd0;
		end
	else if(plus_count != 0)
		begin
		clk_count = clk_count + 16'd1;
		end
end	
endmodule
*/


/**************************module center_ctl*****************************/
//status value
`define		mod_set_freq_h  3'b000
`define		mod_set_freq_l  3'b001
`define		mod_set_dead    3'b010
`define		mod_set_scale   3'b011
`define		mod_set_scan    3'b100
//max &min freq    max & min dead
`define		max_freq		16'd25		// 16'd25000
`define		min_freq		16'd15		// 16'd1500
`define		max_dead 		16'd4		// 16'd200
`define		min_dead		16'd2		//16'd10
`define		freq_step		16'd2		//16'd20
`define		freq_step_long	16'd10		//16'd500
//scan delay in scan mod   each freq last time
//if scan cycle = 40 ms   scan_delay = 13333,if scan cycle = 20 ms scan_delay = 5166
`define		scan_delay		16'd20



module center_ctl(sys_mod,data_up,data_down,areadata,deaddata,plus_occure_enable,
				data_to_display,is_dp_on,freq_scale_data,scale_enable,clk);
	input clk;
	 //signal  from  or to  key_ctl
	input [2:0]sys_mod;      
	input data_up,data_down;
	//signal form or to plus_occure
	output  [15:0]areadata,deaddata;	
	output  plus_occure_enable;//------while it is hight trans data to plus_occure;
	//signal from or to display
	output 	[15:0]data_to_display;
	output  is_dp_on;
	//signal from or to freq_scale
	input  	[15:0]freq_scale_data;
	output	scale_enable;	
	
	reg [15:0] areadata,deaddata,data_to_display;
	reg plus_occure_enable,is_dp_on,scale_enable;
	//sys reg
	
	reg [15:0]freq_data;
	reg [15:0]dead_data;
	//reg [15:0]scale_data;
	reg [15:0]scan_data;
/*************************************************************/	
//deal with signal from key_ctl  and deal with freq_data & dead_data
	always@(posedge clk)
	begin
		if(freq_data <`min_freq)freq_data = `min_freq;
		if(dead_data < `min_dead)dead_data = `min_dead;
		case(sys_mod)
		`mod_set_freq_h:
			begin
			if(data_up)freq_data = freq_data + `freq_step_long;
			if(data_down)freq_data = freq_data - `freq_step_long;
			if(freq_data < `min_freq)freq_data = `min_freq;
			if(freq_data > `max_freq)freq_data = `max_freq;
			end
		`mod_set_freq_l:
			begin
			if(data_up)freq_data = freq_data + `freq_step;
			if(data_down)freq_data = freq_data - `freq_step;
			if(freq_data < `min_freq)freq_data = `min_freq;
			if(freq_data > `max_freq)freq_data = `max_freq;
			end
		`mod_set_dead:
			begin
			if(data_up)dead_data = dead_data + 16'd1;
			if(data_down)dead_data = dead_data - 16'd1;
			if(dead_data < `min_dead)dead_data = `min_dead;
			if(dead_data > `max_dead)dead_data = `max_dead;
			end
		default:;
		endcase
	end
/************************************************/	
//deal with data to display
	always@(posedge clk)
	begin
		case(sys_mod)
		`mod_set_dead:
			begin
			data_to_display = dead_data;
			is_dp_on = 1'b1;			
			end
		`mod_set_scan:
			begin
			data_to_display = scan_data;
			is_dp_on = 1'b0;
			end
		`mod_set_scale:
			begin
			data_to_display = freq_scale_data;
			is_dp_on = 1'b0;
			end
		default:
			begin
			data_to_display = freq_data;
			is_dp_on = 1'b0;
			end
		endcase
	end
	
/***********************************************/	
//deal with data to plus_occure
	always@(negedge clk)
	begin
		plus_occure_enable = 1'b1;
		case(sys_mod)
		`mod_set_scan:
			begin
			areadata = scan_data;
			deaddata = dead_data;
			end
		default:
			begin
			areadata = freq_data;
			deaddata = dead_data;
			end	
		endcase
	end
	//scan
	//deal with scan_data;
	reg [15:0]scandelay;
	always@(posedge clk)
	begin
		if(scan_data < freq_data - 16'd300 || scan_data > freq_data + 16'd300)scan_data = freq_data - 16'd300;
		if(sys_mod == `mod_set_scan)
			begin
			scale_enable = 1'b1;
			if(scandelay == 0)
				begin
				scandelay = `scan_delay;
				scan_data = scan_data + 16'd20;
				end
			else
				scandelay = scandelay - 16'd1;
			end
		else
			scale_enable =1'b0;
	end
	

endmodule