bi_plus_occure_and_scale.v

Verilog HDL 程序 双路脉冲发生器的代码 包含了键盘控制

//2005-8-10
//writen by shao jun wu
//this the first edition (edition 1.0)


// the top layer need  5  child layer

/***********************************************************************/
				//top layer
/************************************************************************/

module bi_plus_occure_and_scale(mod_sel,mod_sure,up,down,
					clock,led,data_out,chip_sel,plus_1,plus_2,plus_in,le373);
		//signal of  key_ctl
		input mod_sel,mod_sure,up,down,clock;
		output [5:0] led;
		//signal of  display
		output [7:0]data_out;
		output [4:0]chip_sel;
		//signal of  plus_occure
		output plus_1,plus_2;	
		//signal of  freq_scale
		input plus_in;
		output le373;
		//signal of  center_ctl

//wires  trans signal between modules x and center_ctl
//module center_ctl(sys_mod,data_up,data_down,areadata,deaddata,plus_occure_enable,
//				data_to_display,is_dp_on,freq_scale_data,scale_enable,clk);
/*	input clk;
	 //signal  from  or to  key_ctl
	input [2:0]sys_mod;      
	input data_up,data_down;
	//signal form or to plus_occure
	output  [15:0]areadata,deaddata;	
	output  plus_occure_enable;//------while it is hight trans data to plus_occure;
	//signal from or to display
	output 	[15:0]data_to_display;
	output  is_dp_on;
	//signal from or to freq_scale
	input  	[15:0]freq_scale_data;
	output	scale_enable;	*/
		wire [2:0]wire_sys_mod;
		wire wire_data_up,wire_data_down;	
		wire [15:0]wire_areadata,wire_deaddata;
		wire wire_plus_occure_enable;
		wire [15:0]wire_data_to_display;
		wire wire_is_dp_on;
		wire [15:0]wire_freq_scale_data;
		wire wire_scale_enable;
	//all the wire is cennect moudle center_ctl and others,so i name the wire with center's io name
	
center_ctl ct_cl(.sys_mod(wire_sys_mod),.data_up(wire_data_up),.data_down(wire_data_down),
				.areadata(wire_areadata),.deaddata(wire_deaddata),.plus_occure_enable(wire_plus_occure_enable),
				.data_to_display(wire_data_to_display),.is_dp_on(wire_is_dp_on),
				.freq_scale_data(wire_freq_scale_data),.scale_enable(wire_scale_enable),.clk(clock));

//module key_ctl(mod_sel,mod_sure,up,down,mod_status_updated,data_up,data_down,led,clk);				
key_ctl keyctl(.mod_sel(mod_sel),.mod_sure(mod_sure),.up(up),.down(down),
				.mod_status_updated(wire_sys_mod),.data_up(wire_data_up),.data_down(wire_data_down),
				.led(led),.clk(clock));

//module display(data_out,chip_sel,data_in,dp_on,clk);
display disp(.data_out(data_out),.chip_sel_out(chip_sel),.data_in(wire_data_to_display),
			.dp_on(wire_is_dp_on),.clk(clock),.le373(le373));
			
//module plus_occure(write_data_enable,freq_data,dead_data,clk,plus_1,plus_2);
plus_occure plusocc(.write_data_enable(wire_plus_occure_enable),.freq_data(wire_areadata),
					.dead_data(wire_deaddata),.clk(clock),.plus_1(plus_1),.plus_2(plus_2));
					
//module freq_scale(enable,plus_in,clk,freq_data);
freq_scale  freqscale(.enable(wire_scale_enable),.plus_in(plus_in),
					.clk(clock),.freq_data(wire_freq_scale_data));

endmodule
/***********************************************************************/
						//child layer
/**************************************************************************/
//module key_ctl    	line :83
//module display    	line :201
//module plus_occure	line :312
//module freq_scale		line :437
//module center_ctl 	line :501
/**************************module key_ctl*******************************/
`define Delay 32'd2   			//10ms delay set as 100000
`define Led_set_freq_h 	5'b00001 //large freq set  eche 500hz;
`define Led_set_freq_l 	5'b00010 //low freq set eche 20 hz;
`define Led_set_dead 	5'b00100 //set dead eche 0.1us;
`define Led_set_scale 	5'b01000//set scale    while in this mod  key up &down is no use
`define Led_set_scan 	5'b10000 //set scan  while in this mod key up &down is no use
//`define Led_ismod_sure 6'b100000 //it light just while the mod that just set is updated to sys .



module key_ctl(mod_sel,mod_sure,up,down,mod_status_updated,data_up,data_down,led,clk);
input mod_sel,mod_sure,up,down,clk;
output [2:0]mod_status_updated;
output data_up,data_down;
output [5:0] led;
reg data_up,data_down;
reg [5:0] led;


reg key_down_flag; //test if has key down;

parameter 	mod_set_freq_h = 3'b000,
			mod_set_freq_l = 3'b001,
			mod_set_dead   = 3'b010,
			mod_set_scale  = 3'b011,
			mod_set_scan   = 3'b100;
			
			
reg [2:0]mod_status;//it will change while the key mod_sel is down. it is link to led
reg [2:0]mod_status_updated;//output reg.it will be changed as mod_status just while the key mod_sure is down
reg [1:0]key_down;//flag which key is down
reg [2:0]nextstatus = mod_set_freq_l;

reg [31:0] delay_time;	

//reg [3:0]keytest;
always@(posedge clk)//test if have key and only one key is down;
	if(	(mod_sel && !mod_sure && !up && !down)||
		(!mod_sel && mod_sure && !up && !down)||
		(!mod_sel && !mod_sure && up && !down)||
		(!mod_sel && !mod_sure && !up && down)	)
		
		key_down_flag = 1'b1;
	else 
		begin
		key_down_flag = 1'b0;
		//delay_time = `Delay;	
		end
	
always@(posedge clk)
begin
	if(key_down_flag == 1'b1)//delay 
		delay_time = delay_time - 31'd1;
	else
		delay_time = `Delay;
		
	if(delay_time == 1)// test which key is down and change the reg mod_status
		begin
			if(mod_sel) mod_status = nextstatus;
			if(mod_sure) mod_status_updated = mod_status;
			if(up && mod_status_updated!=mod_set_scale && mod_status_updated!=mod_set_scan)
				begin
					data_up = 1'b1;
					//#2 data_up = 1'b0;
				end
			if(down && mod_status_updated!=mod_set_scale && mod_status_updated!=mod_set_scan)
				begin
					data_down = 1'b1;
					//#2 data_up =1'b0;
				end
		end
	if(delay_time == 0)
		begin
		data_up = 1'b0;
		data_down = 1'b0;
		delay_time = `Delay;
		end
		
	if(mod_status == mod_status_updated) 
		led[5] = 1'b1;//flag mod is updated
	else
		led[5] = 1'b0;
end


always@(mod_status)
begin
	
	case(mod_status)
	mod_set_freq_h: begin
					nextstatus = mod_set_freq_l;
					led[4:0] = `Led_set_freq_h;//00001
					end
	mod_set_freq_l: begin
					nextstatus = mod_set_dead;
					led[4:0] = `Led_set_freq_l;//00010
					end
	mod_set_dead  : begin
					nextstatus = mod_set_scale;
					led[4:0] = `Led_set_dead;//00100
					end
	mod_set_scale : begin
					nextstatus = mod_set_scan;
					led[4:0] = `Led_set_scale;//01000
					end
	mod_set_scan  : begin
					nextstatus = mod_set_freq_h;
					led[4:0] = `Led_set_scan;//10000
					end
	default		  : begin
					nextstatus = mod_set_freq_l;
					led[4:0] = `Led_set_freq_h;
					end
	endcase
end

endmodule
/**********************module display*************************************/

//gong yang ji
`define code0 8'hc0
`define code1 8'hf9
`define code2 8'ha4
`define code3 8'hb0
`define code4 8'h99
`define code5 8'h92
`define code6 8'h82
`define code7 8'h07
`define code8 8'h80
`define code9 8'h90

//delay of led scan time
//scan cycle = 20ms it should be set as 20ms /(0.01us) = 2* 10E6=32'h1e8480=32'd200000
`define scan_time 32'd4
//gong ying ji
/*
`define code0 8'h3f
`define code1 8'h06
`define code2 8'h5b
`define code3 8'h4f
`define code4 8'h66
`define code5 8'h6d
`define code6 8'h7d
`define code7 8'h07
`define code8 8'h7f
`define code9 8'h6f
*/

module display(data_out,chip_sel_out,data_in,dp_on,clk,le373);
input [15:0]data_in;
input dp_on,clk;
output [7:0]data_out;
output [4:0]chip_sel_out;//gao dui gao wei  di dui di wei
output le373;

reg le373;
reg [4:0]chip_sel;
reg [4:0]chip_sel_out;
reg [7:0]data_out;
reg [7:0]led_code[5:0];
reg [15:0] data_static;
reg [2:0]led_sel;

//reg [31:0]mid;

reg [7:0]num_code[9:0];

always@(posedge clk)
if(num_code[0] != `code0)
	begin
	num_code[0] = `code0;
	num_code[1] = `code1;
	num_code[2] = `code2;
	num_code[3] = `code3;
	num_code[4] = `code4;
	num_code[5] = `code5;
	num_code[6] = `code6;
	num_code[7] = `code7;
	num_code[8] = `code8;
	num_code[9] = `code9;
	end

//change data to led_code
always@(data_static)
begin
	//mid = data_static;
	//chip_sel = 6'b000001;
	//fen li shi jin zhi shu de mei yi wei,bin zhuan huan wei xiang ying de shu chu ma
	led_code[0] = num_code[data_static%10];
	led_code[1] = num_code[(data_static%100)/10];
	led_code[2] = num_code[(data_static%1000)/100];
	led_code[3] = num_code[(data_static%10000)/1000];
	led_code[4] = num_code[(data_static%100000)/10000];
	led_code[5] = num_code[data_static/100000];
	
	
	if(dp_on) led_code[1] = led_code[1] & 8'b10000000;
end
//ouput led_code for cycle
reg [31:0]delay;
always@(posedge clk)
begin
	if(le373 == 1'b0)
		le373 = 1'b1;
	if(data_in!=data_static)
		 data_static = data_in;
	if(delay==0)
		begin
		delay = `scan_time;
		chip_sel = chip_sel<<1;
		if(chip_sel==0) chip_sel=5'b00001;
		chip_sel_out = ~chip_sel;
		
		case(chip_sel)
			5'b00001: led_sel = 3'd0;
			5'b00010: led_sel = 3'd1;
			5'b00100: led_sel = 3'd2;
			5'b01000: led_sel = 3'd3;
			5'b10000: led_sel = 3'd4;
			//6'b100000: led_sel = 3'd5;
			default  : led_sel = 3'd0;
		endcase
		le373 = 1'b0;
		end
	else
		begin
		delay = delay -16'd1;
		end
	data_out = led_code[led_sel];	
end



endmodule