八位的伪随机数产生的verilog文件linear-feedback-shift-register.txt

八位的伪随机数产生的verilog文件linear-feedback-shift-register

发信人: herox (希望), 信区: METech       
标  题: Re: 问一个关于随机数的问题
发信站: BBS 水木清华站 (Fri May 16 11:00:06 2003), 转信

linear-feedback-shift-register
下面是一个八位的伪随机数产生的verilog文件，我想够用了。
// DEFINES
`timescale 1ns/1ns
`define DEL     1               // Clock-to-output delay. Zero
                                        // time delays can be confusing
                                        // and sometimes cause problems.

                                        // These are good tap values for 2 to 32 bits
`define TAP2    2'b11
`define TAP3    3'b101
`define TAP4    4'b1001
`define TAP5    5'b10010
`define TAP6    6'b100001
`define TAP7    7'b1000001
`define TAP8    8'b10001110
`define TAP9    9'b100001000
`define TAP10   10'b1000000100
`define TAP11   11'b10000000010
`define TAP12   12'b100000101001
`define TAP13   13'b1000000001101
`define TAP14   14'b10000000010101
`define TAP15   15'b100000000000001
`define TAP16   16'b1000000000010110
`define TAP17   17'b10000000000000100
`define TAP18   18'b100000000001000000
`define TAP19   19'b1000000000000010011
`define TAP20   20'b10000000000000000100
`define TAP21   21'b100000000000000000010
`define TAP22   22'b1000000000000000000001
`define TAP23   23'b10000000000000000010000
`define TAP24   24'b100000000000000000001101
`define TAP25   25'b1000000000000000000000100
`define TAP26   26'b10000000000000000000100011
`define TAP27   27'b100000000000000000000010011
`define TAP28   28'b1000000000000000000000000100
`define TAP29   29'b10000000000000000000000000010
`define TAP30   30'b100000000000000000000000101001
`define TAP31   31'b1000000000000000000000000000100
`define TAP32   32'b10000000000000000000000001100010

`define BITS 8  // Number of bits in the LFSR
`define TAPS `TAP8      // This must be the taps for the 
                                        // number of bits specified above
`define INIT 1          // This can be any non-zero value
                                        // for initialization of the LFSR

// TOP MODULE
module  random_number(
                data);

// INPUTS
//input                         clk;            // Clock
//input                         reset;          // Reset

// OUTPUTS
output [`BITS-1:0]      data;           // LFSR data

// INOUTS

// SIGNAL DECLARATIONS
reg                     clk;
reg                     reset;
reg [`BITS-1:0] data;

// PARAMETERS
initial 
begin
reset=0;
#4 reset=1;
#2 reset=0;
end

// ASSIGN STATEMENTS
initial 
clk=0;
always
clk= #1 ~clk;

// MAIN CODE

// Look at the rising edge of clock or reset
always @(posedge clk or posedge reset) begin
        if (reset)
                data <= #`DEL `INIT;
        else begin
                // Shift all of the bits left
                data[`BITS-1:1] <= #`DEL data[`BITS-2:0];

`ifdef ADD_ZERO                 // Use this code if data == 0 is required
                // Create the new bit 0
                data[0] <= #`DEL ^(data & `TAPS) ^ ~|data[`BITS-2:0];
`else                                   // Use this code for a standard LFSR
                // Create the new bit 0
                data[0] <= #`DEL ^(data & `TAPS);
`endif

        end
end
initial
#1000 $finish;
endmodule               // LFSR
【 在 lanlizhi (天蓝) 的大作中提到: 】
: lfsr是什么呀？
: 在那里有他的资料呀？
: 谢谢


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