primitives_xilinx.v

pic cpu source code. it is writed in the verilog source code. it can work on the 40Mhz high speed.

	.MG0(in6[0]),
	.MG1(in6[1]),
	.MG2(in6[2]),
	.MG3(in6[3]),
	.MG4(in6[4]),
	.MG5(in6[5]),
	.MG6(in6[6]),
	.MG7(in6[7]),

	.MH0(in7[0]),
	.MH1(in7[1]),
	.MH2(in7[2]),
	.MH3(in7[3]),
	.MH4(in7[4]),
	.MH5(in7[5]),
	.MH6(in7[6]),
	.MH7(in7[7]),

	.S0(sel[0]),
	.S1(sel[1]),
	.S2(sel[2]),

	.O0(out[0]),
	.O1(out[1]),
	.O2(out[2]),
	.O3(out[3]),
	.O4(out[4]),
	.O5(out[5]),
	.O6(out[6]),
	.O7(out[7])	);

// INST_TAG_END

endmodule

/*
// MOD_TAG
module xilinx_mux8_8 (MA,MB,MC,MD,ME,MF,MG,MH,S,O);	// synthesis black_box
input [7 : 0] MA;
input [7 : 0] MB;
input [7 : 0] MC;
input [7 : 0] MD;
input [7 : 0] ME;
input [7 : 0] MF;
input [7 : 0] MG;
input [7 : 0] MH;
input [2 : 0] S;
output [7 : 0] O;

// synopsys translate_off
// synthesis translate_off
	C_MUX_BUS_V1_0 #(
		"00000000",
		1,
		0,
		0,
		0,
		0,
		0,
		1,
		0,
		0,
		0,
		0,
		8,
		0,
		3,
		"00000000",
		0,
		1,
		8)
	inst (
		.MA(MA),
		.MB(MB),
		.MC(MC),
		.MD(MD),
		.ME(ME),
		.MF(MF),
		.MG(MG),
		.MH(MH),
		.S(S),
		.O(O));
// synthesis translate_on
// synopsys translate_on
endmodule
// MOD_TAG_END
*/

// Mux 2:1 11 bits wide
module mux2_11(sel, in0, in1, out);
input		sel;
input	[10:0]	in0, in1;
output	[10:0]	out;

// INST_TAG
xilinx_mux2_11 u0 (
	.MA0(in0[0]),
	.MA1(in0[1]),
	.MA2(in0[2]),
	.MA3(in0[3]),
	.MA4(in0[4]),
	.MA5(in0[5]),
	.MA6(in0[6]),
	.MA7(in0[7]),
	.MA8(in0[8]),
	.MA9(in0[9]),
	.MA10(in0[10]),

	.MB0(in1[0]),
	.MB1(in1[1]),
	.MB2(in1[2]),
	.MB3(in1[3]),
	.MB4(in1[4]),
	.MB5(in1[5]),
	.MB6(in1[6]),
	.MB7(in1[7]),
	.MB8(in1[8]),
	.MB9(in1[9]),
	.MB10(in1[10]),

	.S0(sel),

	.O0(out[0]),
	.O1(out[1]),
	.O2(out[2]),
	.O3(out[3]),
	.O4(out[4]),
	.O5(out[5]),
	.O6(out[6]),
	.O7(out[7]),
	.O8(out[8]),
	.O9(out[9]),
	.O10(out[10])	);
// INST_TAG_END

endmodule

/*
// MOD_TAG
module xilinx_mux2_11 (MA,MB,S,O);	// synthesis black_box
input [10 : 0] MA;
input [10 : 0] MB;
input [0 : 0] S;
output [10 : 0] O;

// synopsys translate_off
// synthesis translate_off
	C_MUX_BUS_V1_0 #(
		"00000000000",
		1,
		0,
		0,
		0,
		0,
		0,
		1,
		0,
		0,
		0,
		0,
		2,
		0,
		1,
		"00000000000",
		0,
		1,
		11)
	inst (
		.MA(MA),
		.MB(MB),
		.S(S),
		.O(O));
// synthesis translate_on
// synopsys translate_on
endmodule
// MOD_TAG_END
*/


// 8bit Add/Sub with carry/borrow out
module add_sub8_co(sub, opa, opb, out, co);
input		sub;
input	[7:0]	opa, opb;
output	[7:0]	out;
output		co;

wire	add;
assign	add = ~sub;

// INST_TAG
xilinx_add_sub8_co u0 (
	.A0(opa[0]),
	.A1(opa[1]),
	.A2(opa[2]),
	.A3(opa[3]),
	.A4(opa[4]),
	.A5(opa[5]),
	.A6(opa[6]),
	.A7(opa[7]),

	.B0(opb[0]),
	.B1(opb[1]),
	.B2(opb[2]),
	.B3(opb[3]),
	.B4(opb[4]),
	.B5(opb[5]),
	.B6(opb[6]),
	.B7(opb[7]),

	.C_OUT(co),
	.ADD(add),

	.S0(out[0]),
	.S1(out[1]),
	.S2(out[2]),
	.S3(out[3]),
	.S4(out[4]),
	.S5(out[5]),
	.S6(out[6]),
	.S7(out[7])	);
// INST_TAG_END

endmodule

/*
// MOD_TAG
module xilinx_add_sub8_co (A,B,C_OUT,ADD,S);	// synthesis black_box
input [7 : 0] A;
input [7 : 0] B;
output C_OUT;
input ADD;
output [7 : 0] S;

// synopsys translate_off
// synthesis translate_off
	C_ADDSUB_V1_0 #(
		2,
		"0000",
		1,
		8,
		0,
		0,
		0,
		1,
		"0",
		8,
		1,
		0,
		1,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		1,
		0,
		0,
		0,
		0,
		0,
		1,
		0,
		0,
		0,
		7,
		0,
		8,
		1,
		"0",
		0,
		1)
	inst (
		.A(A),
		.B(B),
		.C_OUT(C_OUT),
		.ADD(ADD),
		.S(S));
// synthesis translate_on
// synopsys translate_on
endmodule
// MOD_TAG_END
*/

// 11 bit incrementer
module inc11(in, out);
input	[10:0]	in;
output	[10:0]	out;

// INST_TAG
xilinx_inc11 u0 (
	.A0(in[0]),
	.A1(in[1]),
	.A2(in[2]),
	.A3(in[3]),
	.A4(in[4]),
	.A5(in[5]),
	.A6(in[6]),
	.A7(in[7]),
	.A8(in[8]),
	.A9(in[9]),
	.A10(in[10]),

	.S0(out[0]),
	.S1(out[1]),
	.S2(out[2]),
	.S3(out[3]),
	.S4(out[4]),
	.S5(out[5]),
	.S6(out[6]),
	.S7(out[7]),
	.S8(out[8]),
	.S9(out[9]),
	.S10(out[10])	);
// INST_TAG_END

endmodule

/*
// MOD_TAG
module xilinx_inc11 (A,S);	// synthesis black_box
input [10 : 0] A;
output [10 : 0] S;

// synopsys translate_off
// synthesis translate_off
	C_ADDSUB_V1_0 #(
		0,
		"0000",
		1,
		11,
		0,
		0,
		1,
		1,
		"0001",
		11,
		1,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		1,
		0,
		0,
		0,
		10,
		0,
		11,
		1,
		"0",
		0,
		1)
	inst (
		.A(A),
		.S(S));
// synthesis translate_on
// synopsys translate_on
endmodule
// MOD_TAG_END
*/

// 8 bit incrementer
module inc8(in, out);
input	[7:0]	in;
output	[7:0]	out;

// INST_TAG
xilinx_inc8 u0 (
	.A0(in[0]),
	.A1(in[1]),
	.A2(in[2]),
	.A3(in[3]),
	.A4(in[4]),
	.A5(in[5]),
	.A6(in[6]),
	.A7(in[7]),

	.S0(out[0]),
	.S1(out[1]),
	.S2(out[2]),
	.S3(out[3]),
	.S4(out[4]),
	.S5(out[5]),
	.S6(out[6]),
	.S7(out[7])	);
// INST_TAG_END

endmodule

/*
// MOD_TAG
module xilinx_inc8 (A,S);	// synthesis black_box
input [7 : 0] A;
output [7 : 0] S;

// synopsys translate_off
// synthesis translate_off
	C_ADDSUB_V1_0 #(
		0,
		"0000",
		1,
		8,
		0,
		0,
		1,
		1,
		"0001",
		8,
		1,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		1,
		0,
		0,
		0,
		7,
		0,
		8,
		1,
		"0",
		0,
		1)
	inst (
		.A(A),
		.S(S));
// synthesis translate_on
// synopsys translate_on
endmodule
// MOD_TAG_END
*/


// A Basic Synchrounous FIFO (4 entries deep)
module sfifo4x11(clk, push, din, pop, dout);
input		clk;
input		push;
input	[10:0]	din;
input		pop;
output	[10:0]	dout;

reg	[10:0]	stack1, stack2, stack3, stack4;

assign dout = stack1;

always @(posedge clk)
   begin
	if(push)	// PUSH stack
	   begin
		stack4 <= #1 stack3;
		stack3 <= #1 stack2;
	   	stack2 <= #1 stack1;
		stack1 <= #1 din;
	   end
	if(pop)		// POP stack
	   begin
		stack1 <= #1 stack2;
		stack2 <= #1 stack3;
		stack3 <= #1 stack4;
	   end
   end

endmodule


// Synchrounous SRAM
// 128 bytes by 8 bits
// 1 read port, 1 write port
// FOR XILINX VERTEX SERIES
module ssram_128x8(clk, rd_addr, rd_data, we, wr_addr, wr_data);
input		clk;
input	[6:0]	rd_addr;
output	[7:0]	rd_data;
input		we;
input	[6:0]	wr_addr;
input	[7:0]	wr_data;

wire	[7:0]	tmp;


// Alternatively RAMs can be instantiated directly
RAMB4_S8_S8 u0(
	.DOA(	rd_data	),
	.ADDRA(	{2'b0, rd_addr}	),
	.DIA(	8'h00	),
	.ENA(	1'b1	),
	.CLKA(	clk	),
	.WEA(	1'b0	),
	.RSTA(	1'b0	),
	.DOB(	tmp	),
	.ADDRB(	{2'b0, wr_addr}	),
	.DIB(	wr_data	),
	.ENB(	1'b1	),
	.CLKB(	clk	),
	.WEB(	we	),
	.RSTB(	1'b0	)	);


endmodule



// This block is the global Set/Rest for Xilinx VIrtex Serries
// Connect it up as described in Xilinx documentation
// Leave it out for Non Xilinx implementations
module glbl(rst);
input	rst;

wire	GSR;

assign	GSR = rst;

endmodule