📄 primitives_xilinx.v
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/////////////////////////////////////////////////////////////////////
//// ////
//// Mini-RISC-1 ////
//// Prescaler and Wachdog Counter ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// D/L from: http://www.opencores.org/cores/minirisc/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: primitives_xilinx.v,v 1.3 2002/10/01 12:44:24 rudi Exp $
//
// $Date: 2002/10/01 12:44:24 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: primitives_xilinx.v,v $
// Revision 1.3 2002/10/01 12:44:24 rudi
// Tweaked code a bit - trying to get it run faster ...
//
// Revision 1.2 2002/09/27 15:35:40 rudi
// Minor update to newer devices ...
//
//
//
//
//
//
//
//
//
//
//
`timescale 1ns / 10ps
// LIB_TAG
// synopsys translate_off
`include "XilinxCoreLib/C_ADDSUB_V1_0.v"
`include "XilinxCoreLib/C_MUX_BUS_V1_0.v"
`include "XilinxCoreLib/C_COMPARE_V1_0.v"
`include "XilinxCoreLib/C_MUX_BIT_V1_0.v"
`include "XilinxCoreLib/C_MEM_DP_BLOCK_V1_0.v"
`include "XilinxCoreLib/C_REG_FD_V1_0.v"
// synopsys translate_on
// LIB_TAG_END
// Mux 4:1 8 bits wide
module mux4_8(sel, in0, in1, in2, in3, out);
input [1:0] sel;
input [7:0] in0, in1, in2, in3;
output [7:0] out;
// INST_TAG
xilinx_mux4_8 u0 (
.MA0(in0[0]),
.MA1(in0[1]),
.MA2(in0[2]),
.MA3(in0[3]),
.MA4(in0[4]),
.MA5(in0[5]),
.MA6(in0[6]),
.MA7(in0[7]),
.MB0(in1[0]),
.MB1(in1[1]),
.MB2(in1[2]),
.MB3(in1[3]),
.MB4(in1[4]),
.MB5(in1[5]),
.MB6(in1[6]),
.MB7(in1[7]),
.MC0(in2[0]),
.MC1(in2[1]),
.MC2(in2[2]),
.MC3(in2[3]),
.MC4(in2[4]),
.MC5(in2[5]),
.MC6(in2[6]),
.MC7(in2[7]),
.MD0(in3[0]),
.MD1(in3[1]),
.MD2(in3[2]),
.MD3(in3[3]),
.MD4(in3[4]),
.MD5(in3[5]),
.MD6(in3[6]),
.MD7(in3[7]),
.S0(sel[0]),
.S1(sel[1]),
.O0(out[0]),
.O1(out[1]),
.O2(out[2]),
.O3(out[3]),
.O4(out[4]),
.O5(out[5]),
.O6(out[6]),
.O7(out[7]) );
// INST_TAG_END
endmodule
/*
// MOD_TAG
module xilinx_mux4_8 (MA,MB,MC,MD,S,O); // synthesis black_box
input [7:0] MA;
input [7:0] MB;
input [7:0] MC;
input [7:0] MD;
input [1:0] S;
output [7:0] O;
// synopsys translate_off
// synthesis translate_off
C_MUX_BUS_V1_0 #(
"00000000",
1,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
4,
0,
2,
"00000000",
0,
1,
8)
inst (
.MA(MA),
.MB(MB),
.MC(MC),
.MD(MD),
.S(S),
.O(O));
// synthesis translate_on
// synopsys translate_on
endmodule
// MOD_TAG_END
*/
// 8 bit comparator
module cmp8_eq(a,b,eq);
input [7:0] a,b;
output eq;
// INST_TAG
xilinx_cmp8_eq u0 (
.A0(a[0]),
.A1(a[1]),
.A2(a[2]),
.A3(a[3]),
.A4(a[4]),
.A5(a[5]),
.A6(a[6]),
.A7(a[7]),
.B0(b[0]),
.B1(b[1]),
.B2(b[2]),
.B3(b[3]),
.B4(b[4]),
.B5(b[5]),
.B6(b[6]),
.B7(b[7]),
.A_EQ_B(eq) );
// INST_TAG_END
endmodule
/*
// MOD_TAG
module xilinx_cmp8_eq (A,B,A_EQ_B); // synthesis black_box
input [7 : 0] A;
input [7 : 0] B;
output A_EQ_B;
// synopsys translate_off
// synthesis translate_off
C_COMPARE_V1_0 #(
"0",
0,
"0",
1,
1,
0,
0,
1,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
1,
8)
inst (
.A(A),
.B(B),
.A_EQ_B(A_EQ_B));
// synthesis translate_on
// synopsys translate_on
endmodule
// MOD_TAG_END
*/
// MUX 2:1 7 bits wide
module mux2_7(sel, in0, in1, out);
input sel;
input [6:0] in0, in1;
output [6:0] out;
// INST_TAG
xilinx_mux2_7 u0 (
.MA0(in0[0]),
.MA1(in0[1]),
.MA2(in0[2]),
.MA3(in0[3]),
.MA4(in0[4]),
.MA5(in0[5]),
.MA6(in0[6]),
.MB0(in1[0]),
.MB1(in1[1]),
.MB2(in1[2]),
.MB3(in1[3]),
.MB4(in1[4]),
.MB5(in1[5]),
.MB6(in1[6]),
.S0(sel),
.O0(out[0]),
.O1(out[1]),
.O2(out[2]),
.O3(out[3]),
.O4(out[4]),
.O5(out[5]),
.O6(out[6]) );
// INST_TAG_END
endmodule
/*
// MOD_TAG
module xilinx_mux2_7 (MA,MB,S,O); // synthesis black_box
input [6 : 0] MA;
input [6 : 0] MB;
input [0 : 0] S;
output [6 : 0] O;
// synopsys translate_off
// synthesis translate_off
C_MUX_BUS_V1_0 #(
"0000000",
1,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2,
0,
1,
"0000000",
0,
1,
7)
inst (
.MA(MA),
.MB(MB),
.S(S),
.O(O));
// synthesis translate_on
// synopsys translate_on
endmodule
// MOD_TAG_END
*/
// Mux 8:1 1 bit wide
module mux8_1( sel, in, out);
input [2:0] sel;
input [7:0] in;
output out;
// INST_TAG
xilinx_mux8_1 u0 (
.M0(in[0]),
.M1(in[1]),
.M2(in[2]),
.M3(in[3]),
.M4(in[4]),
.M5(in[5]),
.M6(in[6]),
.M7(in[7]),
.S0(sel[0]),
.S1(sel[1]),
.S2(sel[2]),
.O(out));
// INST_TAG_END
endmodule
/*
// MOD_TAG
module xilinx_mux8_1 (M,S,O); // synthesis black_box
input [7 : 0] M;
input [2 : 0] S;
output O;
// synopsys translate_off
// synthesis translate_off
C_MUX_BIT_V1_0 #(
"0",
1,
0,
0,
0,
0,
1,
0,
0,
0,
0,
8,
3,
"0",
0,
1)
inst (
.M(M),
.S(S),
.O(O));
// synthesis translate_on
// synopsys translate_on
endmodule
// MOD_TAG_END
*/
// Mux 2:1 8 bits wide
module mux2_8(sel, in0, in1, out);
input sel;
input [7:0] in0, in1;
output [7:0] out;
// INST_TAG
xilinx_mux2_8 u0(
.MA0(in0[0]),
.MA1(in0[1]),
.MA2(in0[2]),
.MA3(in0[3]),
.MA4(in0[4]),
.MA5(in0[5]),
.MA6(in0[6]),
.MA7(in0[7]),
.MB0(in1[0]),
.MB1(in1[1]),
.MB2(in1[2]),
.MB3(in1[3]),
.MB4(in1[4]),
.MB5(in1[5]),
.MB6(in1[6]),
.MB7(in1[7]),
.S0(sel),
.O0(out[0]),
.O1(out[1]),
.O2(out[2]),
.O3(out[3]),
.O4(out[4]),
.O5(out[5]),
.O6(out[6]),
.O7(out[7]) );
// INST_TAG_END
endmodule
/*
// MOD_TAG
module xilinx_mux2_8 (MA, MB, S, O); // synthesis black_box
input [7 : 0] MA;
input [7 : 0] MB;
input [0 : 0] S;
output [7 : 0] O;
// synopsys translate_off
// synthesis translate_off
C_MUX_BUS_V1_0 #(
"00000000",
1,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2,
0,
1,
"00000000",
0,
1,
8)
inst (
.MA(MA),
.MB(MB),
.S(S),
.O(O));
// synthesis translate_on
// synopsys translate_on
endmodule
// MOD_TAG_END
*/
// Mux 8:1 8 bits wide
module mux8_8(sel, in0, in1, in2, in3, in4, in5, in6, in7, out);
input [2:0] sel;
input [7:0] in0, in1, in2, in3, in4, in5, in6, in7;
output [7:0] out;
// INST_TAG
xilinx_mux8_8 u0 (
.MA0(in0[0]),
.MA1(in0[1]),
.MA2(in0[2]),
.MA3(in0[3]),
.MA4(in0[4]),
.MA5(in0[5]),
.MA6(in0[6]),
.MA7(in0[7]),
.MB0(in1[0]),
.MB1(in1[1]),
.MB2(in1[2]),
.MB3(in1[3]),
.MB4(in1[4]),
.MB5(in1[5]),
.MB6(in1[6]),
.MB7(in1[7]),
.MC0(in2[0]),
.MC1(in2[1]),
.MC2(in2[2]),
.MC3(in2[3]),
.MC4(in2[4]),
.MC5(in2[5]),
.MC6(in2[6]),
.MC7(in2[7]),
.MD0(in3[0]),
.MD1(in3[1]),
.MD2(in3[2]),
.MD3(in3[3]),
.MD4(in3[4]),
.MD5(in3[5]),
.MD6(in3[6]),
.MD7(in3[7]),
.ME0(in4[0]),
.ME1(in4[1]),
.ME2(in4[2]),
.ME3(in4[3]),
.ME4(in4[4]),
.ME5(in4[5]),
.ME6(in4[6]),
.ME7(in4[7]),
.MF0(in5[0]),
.MF1(in5[1]),
.MF2(in5[2]),
.MF3(in5[3]),
.MF4(in5[4]),
.MF5(in5[5]),
.MF6(in5[6]),
.MF7(in5[7]),
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