oaverilogoutscalarize.cpp

openaccess与verilog互相转化时所用的源代码

// *****************************************************************************
// *****************************************************************************
// oaVerilogOutScalarize.cpp
//
// This file contains the implementation of the	oaVerilogOutScalarize class.
//
// *****************************************************************************
// Except as specified in the OpenAccess terms of use of Cadence or Silicon
// Integration Initiative, this	material may not be copied, modified,
// re-published, uploaded, executed, or	istributed in any way, in any medium,
// in whole or in part,	without	prior written permission from Cadence.
//
//		  Copyright 2003-2005 Cadence Design	Systems, Inc.
//			     All Rights	Reserved.
//
//  $Author: shaun $
//  $Revision: 1.5 $
//  $Date: 2005/07/09 17:27:54 $
//  $State: Exp $
// *****************************************************************************
// *****************************************************************************



#include "oaVerilogOutTest.h"



// *****************************************************************************
// oaVerilogOutScalarize::oaVerilogOutScalarize()
//
// This is the constructor for the oaVerilogOutScalarize class.
// *****************************************************************************
oaVerilogOutScalarize::oaVerilogOutScalarize(const oaString &name)
:   oaVerilogOutTest(name)
{
}



// *****************************************************************************
// oaVerilogOutScalarize::buildData()
//
// This function builds the data for the test.
// *****************************************************************************
void
oaVerilogOutScalarize::buildData()
{
    oaLib::create(libN, libStr);
    
    // Build the leaf design.
    oaDesign	*leafDesign = oaDesign::open(libN, oaScalarName(ns, "leaf"),
					     oaScalarName(ns, "abstract"),
					     oaViewType::get(oacNetlist),
					     'w');
    oaModule	*leaf = oaModule::create(leafDesign, oaScalarName(ns, "leaf"));
    oaName	busName(ns, "BUS[7:0]");
    oaModNet	*busNet = oaModNet::create(leaf, busName);
    oaModTerm	*busTerm = oaModTerm::create(busNet, busName);
    oaName	sclrName(ns, "SCALAR");
    oaModNet	*sclrNet = oaModNet::create(leaf, sclrName);
    oaModTerm	*sclrTerm = oaModTerm::create(sclrNet, sclrName);

    leafDesign->setTopModule(leaf);
    leafDesign->save();


    // Build the top design.
    oaDesign	    *topDesign = oaDesign::open(libN, cellN, viewN,
						oaViewType::get(oacNetlist),
						'w');
    oaModule	    *top = oaModule::create(topDesign, cellN);
    oaName	    vssName(ns, "VSS");
    oaModNet	    *vss = oaModNet::create(top, vssName);
    oaModNet	    *bundle = oaModNet::create(top, oaName(ns, "8*VSS"));
    oaScalarName    instName(ns, "I0");
    oaModInst	    *modInst = oaModScalarInst::create(top, leafDesign, 
						       instName);

    oaModInstTerm   *modIterm = oaModInstTerm::create(bundle, modInst, busTerm);
    oaModInstTerm::create(vss, modInst, sclrTerm);

    topDesign->setTopModule(top);
    topDesign->scalarize();

    if (!modIterm->getNet()) {
	tout.print("The module InstTerm to BUS[7:0] should be connected.\n");
    }

    // In the block domain, create another instance and connect the
    // scalar term of the instance to the block VSS net.  Since this is a 
    // change to the bundle net's connectivity, the implicit bundle net
    // should be destroyed.
    oaBlock	*block = topDesign->getTopBlock();
    oaInst	*blockInst = oaScalarInst::create(block, leafDesign,
						  oaScalarName(ns, "I1"),
						  oaTransform(oacR0));
    oaNet	*blockNet = oaNet::find(block, vssName);
    oaTerm	*blockTerm = oaTerm::find(blockInst->getMaster()->getTopBlock(),
					  sclrName);

    oaPoint	origin(0, 0);

    blockInst->setOrigin(origin);
    blockInst->setPlacementStatus(oacFixedPlacementStatus);

    oaInstTerm	*blockInstTerm = oaInstTerm::create(blockNet, blockInst, 
						    blockTerm);
    blockInstTerm->setRouteMethod(oacGeometricRouteMethod);
    blockNet->setSigType(oacGroundSigType);

    if (modIterm->getNet()) {
	tout.print("The module InstTerm to BUS[7:0] should not be connected.\n");
    }

    topDesign->save();
    leafDesign->close();
    topDesign->close();
}



// *****************************************************************************
// oaVerilogOutScalarize::test()
//
// This method is the main entry point for the test.
// *****************************************************************************
oaBoolean
oaVerilogOutScalarize::test()
{
    preTest();
    openOutputFile();

    const oaString  outFile("temp.v");
    MsgAdapter	    msgs;

    try {
	buildData();

	VerilogOut  writer(msgs);
	OptionsOut  &writerOptions = writer.getOptions();

	writerOptions.setFileName(outFile);
	writerOptions.setLibName(libStr);
	writerOptions.setCellName(cellStr);
	writerOptions.setViewName(viewStr);
	writerOptions.enableRecursive(true);
	writerOptions.enableProduceLeaf();

	writer.write();
    }
    catch(Error    &verr) {
	tout.print(verr.getMsg());
	throw;
    }
    catch(oaException	 &oaErr) {
	tout.print((const char*) oaErr.getMsg());
	throw;
    }
    catch(...) {
	tout.print("Caught an exception that was not handled by the writer.\n");
	throw;
    }

    FILE    *moduleFP = fopen((const char*) outFile, "r");

    if (moduleFP) {
	char buf[128];

	while (fgets(buf, 127, moduleFP)) {
	    tout.printLine(buf);
	}
	fclose(moduleFP);
    } else {
	tout.printLine("Unable to open the output file, %s\n",
		       (const char*) outFile);
    }

    closeOutputFile();
    cleanup(libStr);

    return compareOutputByName(getName());
}