oaveriloginleaftest.cpp

openaccess与verilog互相转化时所用的源代码

// *****************************************************************************
// *****************************************************************************
// oaVerilogInLeafTest.cpp
//
// This file contains the implementation of the	oaVerilogInLeafTest class.
//
// *****************************************************************************
// Except as specified in the OpenAccess terms of use of Cadence or Silicon
// Integration Initiative, this	material may not be copied, modified,
// re-published, uploaded, executed, or	istributed in any way, in any medium,
// in whole or in part,	without	prior written permission from Cadence.
//
//		  Copyright 2003-2005 Cadence Design	Systems, Inc.
//			     All Rights	Reserved.
//
//  $Author: sailajad $
//  $Revision: 1.36 $
//  $Date: 2005/08/05 21:58:13 $
//  $State: Exp $
// *****************************************************************************
// *****************************************************************************



#include "oaVerilogInTest.h"



// *****************************************************************************
// oaVerilogInLeafTest::oaVerilogInLeafTest()
//
// This is the constructor for the oaVerilogInLeafTest class.
// *****************************************************************************
oaVerilogInLeafTest::oaVerilogInLeafTest(const oaString	&name,
					 oaBoolean	doNoEMH,
					 oaBoolean	doEMH,
					 oaBoolean	trace)
:   oaVerilogInTest(name, doNoEMH, doEMH, trace)
{
}



// *****************************************************************************
// oaVerilogInLeafTest::buildLeafLib()
//
// This function builds	a library of leaf cells	for Verilog files to reference.
// It must be called after the database	is initialized but before the first
// Verilog file	is read.  The library will be created in the current working
// directory.  If the addOrder argument is true then port order information is 
// added to the terminals (this is the default).  If the addOther argument is
// true, then a third terminal named "other" is created on the leaf cell but
// no position is assigned to this terminal.
// *****************************************************************************
void
oaVerilogInLeafTest::buildLeafLib(const oaString    libPath,
				  const oaString    cellNameStr,
				  const oaString    viewNameStr,
				  oaBoolean	    addOrder,
				  oaBoolean	    addOther,
				  oaBoolean	    doSetTop)
{
    oaNativeNS	    ns;
    oaScalarName    leafLibName(ns, libPath);
    oaScalarName    leafCellName(ns, cellNameStr);
    oaScalarName    leafViewName(ns, viewNameStr);

    oaLib   *lib = oaLib::find(leafLibName);

    if (!lib && oaLib::exists(libPath)) {
	lib = oaLib::open(leafLibName, libPath);
    }

    if (!lib) {
	lib = oaLib::create(leafLibName, libPath);

	oaTech	*tech = oaTech::create(lib);
    
	tech->setDBUPerUU(oaViewType::get(oacMaskLayout), 1000);
	tech->save();
	tech->close();
    }

    if (oaDesign::find(leafLibName, leafCellName, leafViewName)) {
	return;
    }

    oaDesign	*design = oaDesign::open(leafLibName, 
                                         leafCellName,	
					 leafViewName, 
                                         oaViewType::get(oacNetlist), 
                                         'w');
    oaModule	*module = oaModule::create(design, leafCellName);

    if (doSetTop) {
	design->setTopModule(module);
    }

    oaScalarName    in(ns, "in");
    oaModNet	    *net = oaModNet::create(module, in);
    oaModTerm	    *term = oaModTerm::create(net, in, oacInputTermType);

    if (addOrder) {
	term->setPosition(0);
    }

    oaScalarName    out(ns, "out");

    net	= oaModNet::create(module, out);
    term = oaModTerm::create(net, out, oacOutputTermType);

    if (addOrder) {
	term->setPosition(1);
    }

    if (addOther) {
	oaScalarName	aux(ns, "aux");

	net = oaModNet::create(module, aux);
	term  = oaModTerm::create(net, aux, oacInputOutputTermType);
    }

    design->save();
}



// *****************************************************************************
// oaVerilogInLeafTest::buildBusLeaf()
//
// This function builds	a library of leaf cells	for Verilog files to reference.
// The leaf cells built by this function will be block-domain designs that 
// contain scalarized bus terms.
// *****************************************************************************
void
oaVerilogInLeafTest::buildBusLeaf(const oaString    libPath,
				  const oaString    cellNameStr,
				  const oaString    viewNameStr)
{
    oaNativeNS	    ns;
    oaScalarName    leafLibName(ns, libPath);
    oaScalarName    leafCellName(ns, cellNameStr);
    oaScalarName    leafViewName(ns, viewNameStr);

    oaLib   *lib = oaLib::find(leafLibName);

    if (!lib && oaLib::exists(libPath)) {
	lib = oaLib::open(leafLibName, libPath);
    }

    if (!lib) {
	lib = oaLib::create(leafLibName, libPath);

	oaTech	*tech = oaTech::create(lib);
    
	tech->setDBUPerUU(oaViewType::get(oacMaskLayout), 1000);
	tech->save();
	tech->close();
    }

    if (oaDesign::find(leafLibName, leafCellName, leafViewName)) {
	return;
    }

    oaDesign	    *design = oaDesign::open(leafLibName, 
					     leafCellName,	
					     leafViewName, 
					     oaViewType::get(oacMaskLayout), 
					     'w');

    oaBlock	    *block = oaBlock::create(design);
    oaScalarName    Q(ns, "Q");

    for (oaUInt4 i = 0; i < 2; i++) {
	oaBusTermBit::create(oaBusNetBit::create(block, Q, i), Q, i);
    }

    design->save();
}



// *****************************************************************************
// oaVerilogInLeafTest::test()
//
// This method is the main entry point for the test.
// *****************************************************************************
oaBoolean
oaVerilogInLeafTest::test()
{
    preTest();
    buildLeafLib("oaVerilogInTestLeafLib", "scalarLeaf", "prim");
    buildLeafLib("oaVerilogInTestLeafLib", "scalarLeaf", "alt");
    buildLeafLib("oaVerilogInTestLeafLib", "blackBox1", "xxx", false);
    buildLeafLib("oaVerilogInTestLeafLib", "blackBox2", "xxx", false);
    buildLeafLib("oaVerilogInTestLeafLib", "blackBox3", "xxx", false);
    buildLeafLib("oaVerilogInTestLeafLib", "incomplete", "prim", true, true);
    buildLeafLib("oaVerilogInTestLeafLib", "noTop", "prim", false, false, 
	         false);
    buildBusLeaf("oaVerilogInTestLeafLib", "busLeaf", "prim");
    buildBusLeaf("oaVerilogInTestLeafLib", "busLeaf2", "prim");
    buildLeafLib("oaVerilogInTestAltLeafLib", "scalarLeaf", "abstract");
    buildLeafLib("oaVerilogInTestAltLeafLib", "scalarLeaf", "prim");
    buildLeafLib("oaVerilogInTestAltLeafLib", "noOrder", "prim", false);
    buildLeafLib("oaVerilogInTestAltLeafLib", "blackBox1", "prim", false);

    openOutputFile();
    enableCallbacks(true);

    try	{
	oaString    testcase = getPathToData() + ds + getName() + ".v";

	tout.print(starLine);
	tout.print("* Leaf Search\n");
	tout.print(starLine);

	oaNativeNS  ns;
	oaString    myLibName = getName();

	cleanup(myLibName);
	openLib(myLibName);

	MsgAdapter  msgs;

	msgs.setOutFile(tout.outFile);
	msgs.setLogFile(NULL);

	VerilogIn   reader(msgs);
	OptionsIn   &readerOptions = reader.getOptions();
	oaString    topModuleName("top");

	readerOptions.setTopModuleName(topModuleName);
	readerOptions.enableTolerate();
	readerOptions.addLeafLib("oaVerilogInTestLeafLib");
	readerOptions.addLeafLib("oaVerilogInTestAltLeafLib");
	readerOptions.addLeafView("prim");
	readerOptions.addLeafView("alt");
	readerOptions.addFile(testcase);
	readerOptions.setLibName(myLibName);
	readerOptions.enablePurgeLeafs(false);
	reader.parse();

	tout.print("Reader succeeded\n\n\n\n");

	VerilogOut  writer(msgs);
	OptionsOut  &writerOptions = writer.getOptions();
	oaString    tmpFile("tmp.v");

	writerOptions.setFileName((const char*) tmpFile);
	writerOptions.enableRecursive(true);
	writerOptions.setLibName(myLibName);

	oaLib	*lib = oaLib::find(oaScalarName(vns, myLibName));

	lib->getAccess(oacReadLibAccess);

	oaIter<oaCellView>  cvIter(lib->getCellViews());
	oaString	    cellName;
	oaString	    viewName;

	while (oaCellView *cv = cvIter.getNext()) {
	    cv->getCell()->getName(vns, cellName);
	    cv->getView()->getName(vns, viewName);

	    if (cv->getPrimary() && cv->getPrimary()->existsOnDisk()) {
		writerOptions.setCellName(cellName);
		writerOptions.setViewName(viewName);
		writer.write();

		FILE	*fp = fopen((const char*) tmpFile, "r");
		char	buf[128];

		while (fgets(buf, 128, fp)) {
		    tout.print(buf);
		}
	    }
	}

	lib->releaseAccess();
    }
    catch(Error    &verr) {
	tout.print(verr.getMsg());
	closeOutputFile();
	enableCallbacks(false);
	throw;
    }
    catch(oaException	 &oaErr) {
	tout.print((const	char*) oaErr.getMsg());
	closeOutputFile();
	enableCallbacks(false);
	throw;
    }
    catch(...) {
	tout.print("Caught an exception that was not handled by the reader.\n");
	closeOutputFile();
	enableCallbacks(false);
	throw;
    }

    closeOutputFile();
    enableCallbacks(false);
    cleanup("oaVerilogInTestLeafLib");
    cleanup("oaVerilogInTestAltLeafLib");
    cleanup(getName());

    return compareOutputByName(getName());
}