main.cpp

openaccess与verilog互相转化时所用的源代码

// *****************************************************************************
// *****************************************************************************
// main.cpp
//
// This file contains the main for the VerilogIn package's unit tester.
//
// *****************************************************************************
// Except as specified in the OpenAccess terms of use of Cadence or Silicon
// Integration Initiative, this material may not be copied, modified,
// re-published, uploaded, executed, or distributed in any way, in any medium,
// in whole or in part, without prior written permission from Cadence.
//
//                Copyright 2002-2005 Cadence Design Systems, Inc.
//                           All Rights Reserved.
//
//  $Author: shaun $
//  $Revision: 1.59 $
//  $Date: 2005/07/25 18:44:42 $
//  $State: Exp $
// *****************************************************************************
// *****************************************************************************



#include "oaVerilogInTest.h"
#include "oaVerilogOutTest.h"

#if defined(OA_STATIC)
extern "C" void oaDMTurboInit();
extern "C" void oaDMFileSysInit();
#endif



// *****************************************************************************
// oaVerilogTestBuild
// *****************************************************************************
class oaVerilogTestBuild : public oaBuildInfo {
			    oaVerilogTestBuild() : oaBuildInfo("oaVerilogTest",
							       OA_BUILD_NAME,
							       OA_BUILD_TIME,
							       OA_BUILD_NUMBER) {}

  private:
    static oaVerilogTestBuild	buildInfo;
};



// *****************************************************************************
// Initialize Static Members
// *****************************************************************************
oaVerilogTestBuild  oaVerilogTestBuild::buildInfo;




// *****************************************************************************
// oaVerilogTestOptions
// *****************************************************************************
class oaVerilogTestOptions : public oaTestOptions {
  public:
			    oaVerilogTestOptions(const oaString    &usage);
    virtual		    ~oaVerilogTestOptions();

    virtual oaBoolean	    doEMH() const {return _EMH->isSpecified();}
    virtual oaBoolean	    doNoEMH() const {return _noEMH->isSpecified();}
    virtual oaBoolean	    trace() const {return _trace->isSpecified();}
    virtual oaBoolean	    isReaderSpecified() const {return _reader->isSpecified();}
    virtual oaBoolean	    isWriterSpecified() const {return _writer->isSpecified();}
    virtual const oaString  getReaderFile() const {return _reader->getValue();}
    virtual const oaString  getWriterFile() const {return _writer->getValue();}


  protected:
    Switch		    *_EMH;
    Switch		    *_noEMH;
    Switch		    *_trace;
    Arg<oaString>	    *_reader;
    Arg<oaString>	    *_writer;
};



// *****************************************************************************
// oaVerilogTestOptions::oaVerilogTestOptions()
//
// This is the constructor for the oaVerilogTestOptions class.
// *****************************************************************************
oaVerilogTestOptions::oaVerilogTestOptions(const oaString &usage)
:   oaTestOptions(usage)
{
    _EMH = new Switch(*this, "EMH", "[-EMH]", 
		      "Specifies that the Verilog reader used by this test should produce an EMH database");
    _noEMH = new Switch(*this, "noEMH", "[-noEMH]", 
		        "Specifies that the Verilog reader used by this test should not produce an EMH database");
    _trace = new Switch(*this, "trace", "[-trace]", 
			"Specifies that this test should turn on callback tracing while constructing the database");
    _reader = new Arg<oaString>(*this, "reader", "[-reader <verilog-file-name-without-.v-suffix>]",
				"Specifies that this test will invoke the parser with the specified Verilog file as input"
				" and the resulting database will not be compared to a standard", 
				 "");
    _writer = new Arg<oaString>(*this, "writer", "[-writer <verilog-file-name-without-.v-suffix>]",
				"Specifies that this test will invoke the parser with the specified Verilog file as input"
				" and the writer is run on the resulting database with no comparison to a standard", 
				 "");
}



// *****************************************************************************
// oaVerilogTestOptions::~oaVerilogTestOptions()
//
// This is the destructor for the oaVerilogTestOptions class.
// *****************************************************************************
oaVerilogTestOptions::~oaVerilogTestOptions()
{
    delete _EMH;
    delete _noEMH;
    delete _trace;
    delete _reader;
    delete _writer;
}



// *****************************************************************************
// oaVerilogTestApp
// *****************************************************************************
class oaVerilogTestApp : public oaTestApp<oaVerilogTestOptions> {
  public:
			    oaVerilogTestApp();

protected:
    virtual oaBoolean	    validateArgs();
    virtual void	    run();
};



// *****************************************************************************
// oaVerilogTestApp::oaVerilogTestApp()
//
// This is the constructor for oaVerilogTestApp.
// *****************************************************************************
oaVerilogTestApp::oaVerilogTestApp()
:   oaTestApp<oaVerilogTestOptions>("Exercise the OpenAccess Verilog Unit Test Suite")
{
}



// *****************************************************************************
// oaVerilogTestApp::validateArgs()
//
// This method validates the command line arguments.
// *****************************************************************************
oaBoolean
oaVerilogTestApp::validateArgs()
{
    // -reader and -writer options are mutually exclusive.
    if (_args.isReaderSpecified() && _args.isWriterSpecified()) {
	error("-reader and -writer options are mutually exclusive\n");
	return false;
    }

    return oaTestApp<oaVerilogTestOptions>::validateArgs();
}


// *****************************************************************************
// oaVerilogTestApp::run()
//
// This is the run method for oaVerilogTestApp.
// *****************************************************************************

void
oaVerilogTestApp::run()
{  
    oaBoolean doNoEMH = true;
    oaBoolean doEMH = true;

    if (_args.doNoEMH()) {
	doNoEMH = true;
	doEMH = false;
    } else if (_args.doEMH()) {
	doNoEMH = false;
	doEMH = true;
    }

    oaBoolean traceEnabled = _args.trace();

    // Define the tests.
    oaVerilogInTest		IEEEports("IEEEports", doNoEMH, doEMH,
					  traceEnabled);
    oaVerilogInTest		ansiPorts("ansiPorts", doNoEMH, doEMH,
					  traceEnabled);
    oaVerilogInTest		arrayInst("arrayInst", doNoEMH, doEMH,
					  traceEnabled, true);
    oaVerilogInTest		assign("assign", doNoEMH, doEMH, traceEnabled);
    oaVerilogInTest		concat("concat", doNoEMH, doEMH, traceEnabled);
    oaVerilogInTest		connect("connect", doNoEMH, doEMH, traceEnabled);
    oaVerilogInTest		dataType("dataType", doNoEMH, doEMH, 
					 traceEnabled);
    oaVerilogInTest		detectTop("detectTop", doNoEMH, doEMH,
					  traceEnabled);
    oaVerilogInErrorsTest	errorTest("errors", doNoEMH, doEMH);
    oaVerilogInExistingTest	existTest("existing", doNoEMH, doEMH,
					  traceEnabled);
    oaVerilogInTest		forward("forward",  doNoEMH, doEMH, 
					traceEnabled);
    oaVerilogInTest		gaps("gaps", doNoEMH, doEMH, traceEnabled);
    oaVerilogInTest		gates("gates", doNoEMH, doEMH, traceEnabled);
    oaVerilogInTest		globalConn("globalConn", doNoEMH, doEMH, 
				           traceEnabled);
    oaVerilogInTest		hier("hier", doNoEMH, doEMH, traceEnabled);
    oaVerilogInTest		implicitWire("implicitWire", doNoEMH, doEMH, 
					     traceEnabled);
    oaVerilogInLeafTest		leafSearch("leaf", doNoEMH, doEMH, traceEnabled);
    oaVerilogInTest		module("module", doNoEMH, doEMH, traceEnabled);
    oaVerilogInMultiFileTest	multi("multiFile", traceEnabled);
    oaVerilogInTest		nonStruct("nonStruct", doNoEMH, doEMH,
					  traceEnabled);
    oaVerilogInOptionsTest	optionsTest("options", doNoEMH, doEMH);
    oaVerilogInTest		param("param", doNoEMH, doEMH, traceEnabled);
    oaVerilogInTest		portDecls("portDecls", doNoEMH, doEMH,
					  traceEnabled);
    oaVerilogInStubTest		stub("stub", doNoEMH, doEMH, traceEnabled);
    oaVerilogInVliTest		vliTest("vli", doNoEMH, doEMH, traceEnabled);
    oaVerilogInTest		pcr739186("module_decls", doNoEMH, doEMH, 
				          traceEnabled);
    oaVerilogInTest		redefTest("redef", doNoEMH, doEMH, 
					  traceEnabled);
    oaVerilogInTest		pcr776966("pcr776966", doNoEMH, doEMH, 
					  traceEnabled);
    oaVerilogInTest		pcr782725("pcr782725", doNoEMH, doEMH, 
					  traceEnabled);
    oaVerilogInFileSysTest	fileSys("fileSys", doNoEMH, doEMH, 
					traceEnabled);
    oaVerilogInTest		width("width", doNoEMH, doEMH, traceEnabled);

    oaVerilogOutTest		IEEEportsOut("IEEEportsOut");
    oaVerilogOutTest		assignOut("assignOut");
    oaVerilogOutTest		bundle("bundle");
    oaVerilogOutTest		globalTop("globaltop");
    oaVerilogOutTest		hierOut("hierOut");
    oaVerilogOutTest		inOutTest("inoutTest");
    oaVerilogOutOptionsTest	outOptions("outOptions");
    oaVerilogOutExternalTest	externalTest("external");
    oaVerilogOutTest		pcr739428("pcr739428");
    oaVerilogOutUnconnectedTest	unconnected("unconnected");
    oaVerilogOutScalarize	scalarize("scalarize");
    oaVerilogOutUnbound		unbound("unbound");
    oaVerilogOutDesign		designHierOut("designHierOut");
    oaVerilogOutTest		pcr809209("pcr809209");

    oaVerilogAnnotateTest	annotateTest("annotate", traceEnabled);
    oaVerilogCmpTermsTest	cmpTermsTest("cmpTerms");

    oaString readerSampleName(_args.getReaderFile());
    oaString writerSampleName(_args.getWriterFile());

    if (!readerSampleName.isEmpty() || !writerSampleName.isEmpty()) {
	// Run the reader/writer sample tests.
	if (!readerSampleName.isEmpty()) {
	    oaVerilogInSampleTest   sample(readerSampleName, doNoEMH, doEMH,
					   traceEnabled);
	    BaseArg		    *testArg = _args.find("test");

	    testArg->setValue(readerSampleName);
	    testArg->setSpecified();
	    oaTestApp<oaVerilogTestOptions>::run();
	} else if (!writerSampleName.isEmpty()) {
	    oaVerilogOutTest	sample(writerSampleName);
	    BaseArg		*testArg = _args.find("test");

	    testArg->setValue(writerSampleName);
	    testArg->setSpecified();
	    oaTestApp<oaVerilogTestOptions>::run();
	}
    } else {
	oaTestApp<oaVerilogTestOptions>::run();
    }
}



// *****************************************************************************
// main()
//
// This is the main entry point for the oaVerilogTest application.
// *****************************************************************************
int
main(int    argc, 
     char   *argv[])
{
    // Initialize required OpenAccess modules.
    oaDesignInit();

#if defined(OA_STATIC)
    oaDMTurboInit();
    oaDMFileSysInit();
#endif

    oaVerilogTestApp app;

    try {
	app.main(argc, argv);
    }

    catch (oaException	&excp) {
	app.error(excp.getMsg());
    }

    return app.getExitStatus();
}