oaveriloginexistingtest.cpp

openaccess与verilog互相转化时所用的源代码

// *****************************************************************************
// *****************************************************************************
// oaVerilogInExistingTest.cpp
//
// This file contains the implementation of the	test driver for	Verilog reader's
// existing data test.
//
// *****************************************************************************
// Except as specified in the OpenAccess terms of use of Cadence or Silicon
// Integration Initiative, this	material may not be copied, modified,
// re-published, uploaded, executed, or	istributed in any way, in any medium,
// in whole or in part,	without	prior written permission from Cadence.
//
//		  Copyright 2003-2005 Cadence Design	Systems, Inc.
//			     All Rights	Reserved.
//
//  $Author: shaun $
//  $Revision: 1.26 $
//  $Date: 2005/06/23 05:02:01 $
//  $State: Exp $
// *****************************************************************************
// *****************************************************************************



#include "oaVerilogInTest.h"
#ifndef	WINDOWS
#include <sys/types.h>
#include <sys/stat.h>
#endif




// *****************************************************************************
// oaVerilogInExistingTest::oaVerilogInExistingTest
//
// This is the constructor for the oaVerilogInExistingTest.
// *****************************************************************************
oaVerilogInExistingTest::oaVerilogInExistingTest(const oaString  &name,
						 oaBoolean	 doNoEMH,
						 oaBoolean	 doEMH,
						 oaBoolean	 trace)
: oaVerilogInTest(name, doNoEMH, doEMH, trace)
{
}



// *****************************************************************************
// oaVerilogInExistingTest::buildData()
//
// This function builds	some existing data that the reader will modify and/or
// overwrite as it reads the Verilog input.
// *****************************************************************************
void
oaVerilogInExistingTest::buildData(const oaString   &libPath,
				   const oaString   &cellNameStr,
				   const oaString   &viewNameStr)
{
    oaNativeNS	    ns;
    oaScalarName    exLibName(ns, libPath);
    oaScalarName    exCellName(ns, cellNameStr);
    oaScalarName    exViewName(ns, viewNameStr);
    LibMgrOptions   defaultOptions;

    oaLib	*lib    = LibMgr::create(exLibName, libPath, defaultOptions);
    oaDesign	*design = oaDesign::open(exLibName, exCellName, exViewName,
					 oaViewType::get(oacNetlist), 'w');
    oaModule	*module = oaModule::create(design, exCellName);

    design->setTopModule(module);

    oaScalarName    in(ns, "in");
    oaModNet	    *net = oaModNet::create(module, in);
    oaModTerm	    *term = oaModTerm::create(net, in, oacInputTermType);

    term->setPosition(0);

    oaScalarName    out(ns, "out");

    net	= oaModNet::create(module, out);
    term = oaModTerm::create(net, out, oacOutputTermType);
    term->setPosition(1);

    oaScalarName    tri(ns, "t");

    net	= oaModNet::create(module, tri);
    term = oaModTerm::create(net, tri, oacTristateTermType);
    term->setPosition(2);

    oaModScalarInst::create(module, exLibName, oaScalarName(ns, "leaf"),
			    exViewName, oaScalarName(ns, "original"));

    design->save();

    oaDesign	*d = oaDesign::find(exLibName, exCellName, exViewName);

    if (!d) {
	throw;
    }
}


// *****************************************************************************
// oaVerilogInExistingTest::test()
//
// This method is the main entry point for the test.
// *****************************************************************************
oaBoolean
oaVerilogInExistingTest::test()
{
    preTest();
    openOutputFile();

    try	{
	oaString    testcase = getPathToData() + ds + getName() + ".v";

	buildData(getName() + "_designEMH", getName(), "netlist");
	buildData(getName() + "_design", getName(), "netlist");

	enableCallbacks(true);

	tout.printLine((const char*) starLine);
	tout.printLine("* Append Mode (should throw exception)\n");
	tout.printLine((const char*) starLine);

	MsgAdapter  appendMsgs;
	VerilogIn   append(appendMsgs);
	OptionsIn   &appendOptions = append.getOptions();

	appendOptions.enableTolerate();
	appendOptions.enableFileAndLine(fullErrorMessages);
	appendOptions.setLibName(getName() + "_design");
	appendOptions.addFile(testcase);
	append.enableDesignPerMod(true);

	try {
	    append.parse();
	    tout.print("Failed to catch expected exception.\n");
	}
	catch (oaException  &excp) {
	    tout.print("Caught exception: %s\n", (const char*) excp.getMsg());
	}

	tout.printLine((const char*) starLine);
	tout.printLine("* Overwrite Mode\n");
	tout.printLine((const char*) starLine);

	MsgAdapter  overwrtMgs;
	VerilogIn   ovrwrt(overwrtMgs);
	OptionsIn   &ovrwrtOptions = ovrwrt.getOptions();

	ovrwrtOptions.enableTolerate();
	ovrwrtOptions.enableFileAndLine(fullErrorMessages);
	ovrwrtOptions.enableOverwrite(true);
	testReader(ovrwrt, testcase);
    }
    catch(Error    &verr) {
	tout.print(verr.getMsg());
	closeOutputFile();
	enableCallbacks(false);
	throw;
    }
    catch(oaException	 &oaErr) {
	tout.print((const char*) oaErr.getMsg());
	closeOutputFile();
	enableCallbacks(false);
	throw;
    }
    catch(...) {
	tout.print("Caught an exception that was not handled by the reader.\n");
	closeOutputFile();
	enableCallbacks(false);
	throw;
    }

    cleanup(getName() + "_designX");
    closeOutputFile();
    enableCallbacks(false);

    return compareOutputByName(getName());
}