oaverilogoutexternaltest.cpp

openaccess与verilog互相转化时所用的源代码

    oaDesign	*orMaster = buildOr(myLibName);
    oaDesign	*ha1Master = buildHalfAdder(myLibName);
    oaDesign	*ha2Master = ha1Master;
    oaDesign	*leafMaster = buildLeaf(myLibName);

    oaModScalarInst *ha1 = oaModScalarInst::create(module, ha1Master);
    oaModScalarInst *ha2 = oaModScalarInst::create(module, ha2Master);
    oaModScalarInst *extra = oaModScalarInst::create(module, ha1Master, 
						     oaScalarName(ns, "extra"));
    oaModScalarInst *or0 = oaModScalarInst::create(module, orMaster);
    oaModScalarInst *leaf = oaModScalarInst::create(module, leafMaster);

    oaModBusNet	    *sum = oaModBusNet::create(module, 
					       oaVectorName(ns, "sum[0:3]"));

    oaModScalarNet  *c1 = oaModScalarNet::create(module, 
					         oaScalarName(ns, "c1"));
    oaModScalarNet  *c2 = oaModScalarNet::create(module, 
					         oaScalarName(ns, "c2"));
    oaModScalarNet  *tie0 = oaModScalarNet::create(module, 
					           oaScalarName(ns, "tie0"),
						   oacTieLoSigType);
    oaModBusNet	    *x0_3 = oaModBusNet::create(module,
					        oaVectorName(ns, "x[0:3]"));
    oaModBusNet	    *x0_1 = oaModBusNet::create(module,
					        oaVectorName(ns, "x[0:1]"));
    oaModBusNetBit  *x0 = oaModBusNetBit::create(module,
					         oaVectorBitName(ns, "x[0]"));
    oaModBusNetBit  *x1 = oaModBusNetBit::create(module,
					         oaVectorBitName(ns, "x[1]"));
    oaModBusNetBit  *x2 = oaModBusNetBit::create(module,
					         oaVectorBitName(ns, "x[2]"));
    oaModBusNetBit  *x3 = oaModBusNetBit::create(module,
					         oaVectorBitName(ns, "x[3]"));

    tie0->setGlobal(true);

    oaModScalarNet  *low = oaModScalarNet::create(module,
						  oaScalarName(ns, "LOW"),
						  oacTieLoSigType);
    oaModScalarNet  *zLow = oaModScalarNet::create(module,
						   oaScalarName(ns, "zLow"));

    low->setGlobal(true);
    zLow->makeEquivalent(low);
    low->setPreferredEquivalent();

    oaModScalarNet  *high = oaModScalarNet::create(module,
						   oaScalarName(ns, "HIGH"),
						   oacTieHiSigType);
    oaModScalarNet  *zHigh = oaModScalarNet::create(module,
						    oaScalarName(ns, "zHigh"));
    high->setGlobal(true);
    zHigh->makeEquivalent(high);
    high->setPreferredEquivalent();

    oaModInstTerm::create(x0_1, leaf, oaVectorName(ns, "in[0:1]"));
    oaModInstTerm::create(x0, leaf, oaVectorBitName(ns, "in[0]"));
    oaModInstTerm::create(x1, leaf, oaVectorBitName(ns, "in[1]"));
    oaModInstTerm::create(x2, leaf, oaVectorBitName(ns, "in[2]"));
    oaModInstTerm::create(x3, leaf, oaVectorBitName(ns, "in[3]"));

    oaBundleName    bundleN1;

    bundleN1.append(oaScalarName(ns, "tie0"));
    bundleN1.append(oaScalarName(ns, "cin"));
    bundleN1.append(oaScalarName(ns, "tie0"));
    bundleN1.append(oaScalarName(ns, "cin"));

    oaModBundleNet  *bundle = oaModBundleNet::create(module, bundleN1);

    oaModInstTerm::create(bundle, leaf, oaVectorName(ns, "out[0:3]"));

    oaModInstTerm::create(in1, ha1, oaVectorName(ns, "in1[0:3]"));
    oaModInstTerm::create(in2, ha1, oaVectorName(ns, "in2[0:3]"));
    oaModInstTerm::create(sum, ha1, oaVectorName(ns, "out[0:3]"));
    oaModInstTerm::create(c1, ha1, oaScalarName(ns, "carry"));

    oaModInstTerm::create(sum, ha2, oaVectorName(ns, "in1[0:3]"));

    oaBundleName    bundleN2;

    bundleN2.append(oaScalarName(ns, "tie0"), 3);
    bundleN2.append(oaScalarName(ns, "cin"));
    bundle = oaModBundleNet::create(module, bundleN2);

    oaModInstTerm::create(bundle, ha2, oaVectorName(ns, "in2[0:3]"));
    oaModInstTerm::create(out_0, ha2, oaVectorBitName(ns, "out[0]"));
    oaModInstTerm::create(out_1, ha2, oaVectorBitName(ns, "out[1]"));
    oaModInstTerm::create(out_2, ha2, oaVectorBitName(ns, "out[2]"));
    oaModInstTerm::create(out_3, ha2, oaVectorBitName(ns, "out[3]"));
    oaModInstTerm::create(c2, ha2, oaScalarName(ns, "carry"));

    oaModInstTerm::create(c2, or0, oaScalarName(ns, "in1"));
    oaModInstTerm::create(c1, or0, oaScalarName(ns, "in2"));
    oaModInstTerm::create(cout, or0, oaScalarName(ns, "out"));

    // The x0 connection is deliberately repeated in the extra instance.
    oaModInstTerm::create(out_0, extra, oaVectorBitName(ns, "out[0]"));
    oaModInstTerm::create(out_1, extra, oaVectorBitName(ns, "out[1]"));
    oaModInstTerm::create(x0, extra, oaVectorBitName(ns, "out[2]"));
    oaModInstTerm::create(x0, extra, oaVectorBitName(ns, "out[3]"));
    
    oaBundleName    hiloBundleN;

    hiloBundleN.append(oaScalarName(ns, "HIGH"));
    hiloBundleN.append(oaScalarName(ns, "LOW"));
    hiloBundleN.append(oaScalarName(ns, "HIGH"));
    hiloBundleN.append(oaScalarName(ns, "LOW"));

    oaModBundleNet  *hilo = oaModBundleNet::create(module, hiloBundleN);

    // This connection will not be bound because the bits are reversed.
    oaModInstTerm::create(hilo, extra, oaVectorName(ns, "in1[3:0]"));

    oaBundleName    lohiBundleN;

    lohiBundleN.append(oaScalarName(ns, "LOW"));
    lohiBundleN.append(oaScalarName(ns, "LOW"));
    lohiBundleN.append(oaScalarName(ns, "HIGH"));
    lohiBundleN.append(oaScalarName(ns, "HIGH"));

    oaModBundleNet  *lohi = oaModBundleNet::create(module, lohiBundleN);

    // This connection will be bound.
    oaModInstTerm::create(lohi, extra, oaVectorName(ns, "in2[0:3]"));


    design->scalarize();
    design->save();

    ha1Master->close();
    orMaster->close();
    design->close();
}



// *****************************************************************************
// oaVerilogOutExternalTest::buildLib()
//
// This function builds	a library of cells for the writer to operate on.
// *****************************************************************************
void
oaVerilogOutExternalTest::buildLib(const oaString   libPath,
				   const oaString   cellName,
				   const oaString   viewName)
{
    oaScalarName    myLibName(ns, libPath);

    oaLib   *lib = oaLib::find(myLibName);

    if (!lib && oaLib::exists(libPath)) {
	oaLib::open(myLibName, libPath);
    }

    if (!lib) {
	lib = oaLib::create(myLibName, libPath);
    }

    buildFullAdder(myLibName, oaScalarName(ns, cellName), 
	           oaScalarName(ns, viewName));
}



// *****************************************************************************
// oaVerilogOutExternalTest::test()
//
// This method is the main entry point for the test.
// *****************************************************************************
oaBoolean
oaVerilogOutExternalTest::test()
{
    preTest();
    openOutputFile();

    const oaString  outFile("temp.v");
    MsgAdapter	    msgs;

    try {
	const oaString	lib("library");
	const oaString	cell("fullAdder");
	const oaString	view("netlist");

	buildLib(lib, cell, view);

	VerilogOut  writer(msgs);
	OptionsOut  &writerOptions = writer.getOptions();

	writerOptions.setFileName(outFile);
	writerOptions.setLibName(lib);
	writerOptions.setCellName(cell);
	writerOptions.setViewName(view);
	writerOptions.enableRecursive(true);
	writerOptions.enableProduceLeaf();

	writer.write();
	copyFileToOutput(outFile);
    }
    catch(Error    &verr) {
	tout.print(verr.getMsg());
	closeOutputFile();
	throw;
    }
    catch(oaException	 &oaErr) {
	tout.print((const char*) oaErr.getMsg());
	closeOutputFile();
	throw;
    }
    catch(...) {
	tout.print("Caught an exception that was not handled by the writer.\n");
	closeOutputFile();
	throw;
    }

    closeOutputFile();
    cleanup("library");

    return compareOutputByName(getName());
}