oaverilogoutexternaltest.cpp

openaccess与verilog互相转化时所用的源代码

// *****************************************************************************
// *****************************************************************************
// oaVerilogOutExternalTest.cpp
//
// This file contains the implementation of the	oaVerilogOutExternalTest class.
//
// *****************************************************************************
// Except as specified in the OpenAccess terms of use of Cadence or Silicon
// Integration Initiative, this	material may not be copied, modified,
// re-published, uploaded, executed, or	distributed in any way, in any medium,
// in whole or in part,	without	prior written permission from Cadence.
//
//		  Copyright 2003-2005 Cadence Design Systems, Inc.
//			     All Rights	Reserved.
//
//  $Author: shaun $
//  $Revision: 1.26 $
//  $Date: 2005/07/09 17:35:33 $
//  $State: Exp $
// *****************************************************************************
// *****************************************************************************



#include "oaVerilogOutTest.h"



// *****************************************************************************
// oaVerilogOutExternalTest::oaVerilogOutExternalTest()
//
// This is the constructor for the oaVerilogOutExternalTest class.
// *****************************************************************************
oaVerilogOutExternalTest::oaVerilogOutExternalTest(const oaString   &name)
:   oaVerilogOutTest(name)
{
}



// *****************************************************************************
// oaVerilogOutExternalTest::buildOr()
//
// This function builds	an abstract "or" cell.
// *****************************************************************************
oaDesign*
oaVerilogOutExternalTest::buildOr(const oaScalarName	&myLibName)
{
    oaScalarName    cellName(ns, "or2");
    oaScalarName    viewName(ns, "abstract");

    oaDesign	*design = oaDesign::open(myLibName, cellName, viewName, 
                                         oaViewType::get(oacNetlist), 'w');

    oaModule	*module = oaModule::create(design, cellName);

    design->setTopModule(module);

    oaScalarName    in1(ns, "in1");
    oaScalarName    in2(ns, "in2");
    oaScalarName    out(ns, "out");

    oaModScalarTerm::create(oaModScalarNet::create(module, in1), in1, 
			    oacInputTermType);
    oaModScalarTerm::create(oaModScalarNet::create(module, in2), in2, 
			    oacInputTermType);
    oaModScalarTerm::create(oaModScalarNet::create(module, out), out, 
			    oacOutputTermType);

    design->scalarize();
    design->save();

    return design;
}



// *****************************************************************************
// oaVerilogOutExternalTest::buildHalfAdder()
//
// This function builds	an abstract "HalfAdder" cell.
// *****************************************************************************
oaDesign*
oaVerilogOutExternalTest::buildHalfAdder(const oaScalarName &myLibName)
{
    oaScalarName    cellName(ns, "halfAdder");
    oaScalarName    viewName(ns, "abstract");

    oaDesign	*design = oaDesign::open(myLibName, cellName, viewName, 
                                         oaViewType::get(oacNetlist), 'w');

    oaModule	*module = oaModule::create(design, cellName);

    design->setTopModule(module);

    oaVectorName    in1(ns, "in1[0:3]");
    oaVectorName    in2(ns, "in2[0:3]");
    oaVectorName    out(ns, "out[0:3]");
    oaScalarName    carry(ns, "carry");
    
    oaModBusTerm::create(oaModBusNet::create(module, in1), in1, 
			 oacInputTermType);
    oaModBusTerm::create(oaModBusNet::create(module, in2), in2,
			 oacInputTermType);
    oaModBusTerm::create(oaModBusNet::create(module, out), out,
			 oacOutputTermType);
    oaModScalarTerm::create(oaModScalarNet::create(module, carry), carry, 
			    oacOutputTermType);

    design->scalarize();
    design->save();

    return design;
}



// *****************************************************************************
// oaVerilogOutExternalTest::buildLeaf()
//
// This function builds	an abstract "Leaf" cell.  The "Leaf" cell contains
// multi-bit, overlapping terminals.
// *****************************************************************************
oaDesign*
oaVerilogOutExternalTest::buildLeaf(const oaScalarName	&myLibName) 
{
    oaScalarName    cellName(ns, "leaf");
    oaScalarName    viewName(ns, "abstract");

    oaDesign	*design = oaDesign::open(myLibName, cellName, viewName, 
                                         oaViewType::get(oacNetlist), 'w');

    oaModule	*module = oaModule::create(design, cellName);

    design->setTopModule(module);

    oaVectorName    in1(ns, "in[0:3]");
    oaVectorName    in2(ns, "in[0:1]");
    oaVectorName    out(ns, "out[0:3]");
    oaVectorBitName z(ns, "z[0]");
    oaVectorBitName y(ns, "y[1]");
    oaVectorBitName x(ns, "x[2]");
    oaVectorBitName w(ns, "w[3]");
    oaBundleName    bundleA;
    oaBundleName    bundleB;
    oaBundleName    bundleC;

    bundleA.append(oaScalarName(ns, "a"));
    bundleA.append(oaScalarName(ns, "b"));
    bundleA.append(oaScalarName(ns, "c"));

    bundleB.append(oaScalarName(ns, "d"));
    bundleB.append(oaScalarName(ns, "e"));

    bundleC.append(oaScalarName(ns, "f"));
    bundleC.append(oaScalarName(ns, "g"));

    oaModBusTerm::create(oaModBusNetBit::create(module, z), z,
			 oacInputOutputTermType);
    oaModBundleTerm::create(oaModBundleNet::create(module, bundleB), bundleB,
			    oacInputOutputTermType);
    oaModBusTerm::create(oaModBusNet::create(module, in1), in1, 
			 oacInputTermType);
    oaModBusTerm::create(oaModBusNetBit::create(module, w), w,
			 oacInputOutputTermType);
    oaModBusTerm::create(oaModBusNet::create(module, in2), in2, 
			 oacInputTermType);
    oaModBundleTerm::create(oaModBundleNet::create(module, bundleC), bundleC,
			    oacInputOutputTermType);
    oaModBusTerm::create(oaModBusNetBit::create(module, y), y,
			 oacInputOutputTermType);
    oaModBusTerm::create(oaModBusNet::create(module, out), out, 
			 oacOutputTermType);
    oaModBusTerm::create(oaModBusNetBit::create(module, x), x,
			 oacInputOutputTermType);
    oaModBundleTerm::create(oaModBundleNet::create(module, bundleA), bundleA,
			    oacInputOutputTermType);

    design->scalarize();
    design->save();

    return design;
}



// *****************************************************************************
// oaVerilogOutExternalTest::buildFullAdder()
//
// This function builds	an abstract "FullAdder" cell.
// *****************************************************************************
void
oaVerilogOutExternalTest::buildFullAdder(const oaScalarName &myLibName,
					 const oaScalarName &cellName,
					 const oaScalarName &viewName)
{
    oaDesign	*design = oaDesign::open(myLibName, cellName, viewName, 
                                         oaViewType::get(oacNetlist), 'w');

    oaModule	*module = oaModule::create(design, cellName);

    design->setTopModule(module);

    oaModBusNet	    *in1 = oaModBusNet::create(module, 
					       oaVectorName(ns, "in1[0:3]"));
    oaModBusNet	    *in2 = oaModBusNet::create(module, 
					       oaVectorName(ns, "in2[0:3]"));
    oaModBusNet	    *out = oaModBusNet::create(module, 
					       oaVectorName(ns, "out[0:3]"));
    oaModBusNetBit  *out_0 = oaModBusNetBit::create(module, 
						    oaVectorBitName(ns, "out[0]"));
    oaModBusNetBit  *out_1 = oaModBusNetBit::create(module, 
						    oaVectorBitName(ns, "out[1]"));
    oaModBusNetBit  *out_2 = oaModBusNetBit::create(module, 
						    oaVectorBitName(ns, "out[2]"));
    oaModBusNetBit  *out_3 = oaModBusNetBit::create(module, 
						    oaVectorBitName(ns, "out[3]"));
    oaModScalarNet  *cin = oaModScalarNet::create(module, 
						  oaScalarName(ns, "cin"));
    oaModScalarNet  *cout = oaModScalarNet::create(module, 
						   oaScalarName(ns, "cout"));

    oaModBusTerm::create(in1, oaVectorName(ns, "in1[0:3]"), oacInputTermType);
    oaModBusTerm::create(in2, oaVectorName(ns, "in2[0:3]"), oacInputTermType);
    oaModScalarTerm::create(cin, oaScalarName(ns, "cin"), oacInputTermType);
    oaModScalarTerm::create(cout, oaScalarName(ns, "cout"), oacOutputTermType);
    oaModBusTerm::create(out, oaVectorName(ns, "out[0:3]"), oacOutputTermType);