nonstruct.ref

openaccess与verilog互相转化时所用的源代码

******************************************************************************
* No Explode, No EMH
******************************************************************************
Warning: Config declarations are not implemented
Warning: Library text is not implemented
Warning: Real declarations are not implemented
Warning: Parameter arrays not implemented
Warning: Genvar declarations are not implemented
Warning: Binary operators are not implemented
Warning: Binary operators are not implemented
Warning: Binary operators are not implemented
Warning: Generate blocks are not implemented
Contents of nonStruct_design.gen.netlist
    Contents of TOP module gen
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            Net: 'in1[0]' (ModBusNetBit)
                Equiv:	out[0]
            Net: 'in2[2:0]' (ModBusNet)
            Net: 'x[10:12]' (ModBusNet)
            Net: 'y[10:8]' (ModBusNet)
            Net: 'z[10:3]' (ModBusNet)



Warning: Time declarations are not implemented
Contents of nonStruct_design.pCell.netlist
    Contents of TOP module pCell
            Term: 'out' (ModScalarTerm)
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        	Net:		'in2'
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            Net: 'out' (ModScalarNet)
            Net: 'in1' (ModScalarNet)
            Net: 'in2' (ModScalarNet)



Contents of nonStruct_design.child.netlist
    Contents of TOP module child
            Term: 'a' (ModScalarTerm)
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        	NumBits:	1
        	Net:		'a'
        	Position:	0
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            Net: 'a' (ModScalarNet)
            Net: 'y' (ModScalarNet)
            Net: 'powr' (ModScalarNet)
            Net: 'grnd' (ModScalarNet)
            Net: 'CK' (ModScalarNet)



Warning: Function calls are not implemented
Warning: Time declarations are not implemented
Warning: Function calls are not implemented
Warning: Realtime declarations are not implemented
Warning: Time declarations are not implemented
Warning: Realtime declarations are not implemented
Warning: Integer arrays are not implemented
Warning: Multi-dimensional registers are not implemented
Warning: Function calls are not implemented
Warning: Function calls are not implemented
Warning: Function calls are not implemented
Warning: Function calls are not implemented
Warning: Initial statements are not implemented
Warning: Unary operators are not implemented
Warning: Event declarations are not implemented
Warning: Binary operators are not implemented
Warning: Binary operators are not implemented
Warning: Unary operators are not implemented
Warning: Binary operators are not implemented
Warning: Binary operators are not implemented
Warning: Binary operators are not implemented
Warning: min:typ:max expressions always evaluate to "typ"
Warning: Unary operators are not implemented
Warning: Function calls are not implemented
Warning: Binary operators are not implemented
Warning: Always blocks are not implemented
Warning: Binary operators are not implemented
Warning: Binary operators are not implemented
Warning: Binary operators are not implemented
Warning: Binary operators are not implemented
Warning: Binary operators are not implemented
Warning: Binary operators are not implemented
Warning: Binary operators are not implemented
Warning: Function declarations are not implemented
Contents of nonStruct_design.top.netlist
    Contents of TOP module top
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            Net: 'pc[12:0]' (ModBusNet)
            Net: 'acc[12:0]' (ModBusNet)
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            Net: 'y' (ModScalarNet)
            Net: 'z' (ModScalarNet)
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        ModInstTerm:
        	Net:	z
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	Posit:	3 (bound to 'grnd')



Reader succeeded



******************************************************************************
* No Explode, EMH
******************************************************************************
Warning: Config declarations are not implemented
Warning: Library text is not implemented
Warning: Real declarations are not implemented
Warning: Parameter arrays not implemented
Warning: Genvar declarations are not implemented
Warning: Binary operators are not implemented
Warning: Binary operators are not implemented
Warning: Binary operators are not implemented
Warning: Generate blocks are not implemented
Warning: Time declarations are not implemented
Warning: Function calls are not implemented
Warning: Time declarations are not implemented
Warning: Function calls are not implemented
Warning: Realtime declarations are not implemented
Warning: Time declarations are not implemented
Warning: Realtime declarations are not implemented
Warning: Integer arrays are not implemented
Warning: Multi-dimensional registers are not implemented
Warning: Function calls are not implemented
Warning: Function calls are not implemented
Warning: Function calls are not implemented
Warning: Function calls are not implemented
Warning: Initial statements are not implemented
Warning: Unary operators are not implemented
Warning: Event declarations are not implemented
Warning: Binary operators are not implemented
Warning: Binary operators are not implemented
Warning: Unary operators are not implemented
Warning: Binary operators are not implemented
Warning: Binary operators are not implemented
Warning: Binary operators are not implemented
Warning: min:typ:max expressions always evaluate to "typ"
Warning: Unary operators are not implemented
Warning: Function calls are not implemented
Warning: Binary operators are not implemented
Warning: Always blocks are not implemented
Warning: Binary operators are not implemented
Warning: Binary operators are not implemented
Warning: Binary operators are not implemented
Warning: Binary operators are not implemented
Warning: Binary operators are not implemented
Warning: Binary operators are not implemented
Warning: Binary operators are not implemented
Warning: Function declarations are not implemented
Info: The top module is top
Contents of nonStruct_designEMH.top.netlist
    Contents of module gen
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        	TermType:	input
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        	Net:		'in1[2:0]'
        	Position:	1
            Term: 'out[0:2]' (ModBusTerm)
        	TermType:	output
        	NumBits:	3
        	Net:		'out[0:2]'
        	Position:	0
            Net: 'z[10:3]' (ModBusNet)
            Net: 'y[10:8]' (ModBusNet)
            Net: 'x[10:12]' (ModBusNet)
            Net: 'in2[2:0]' (ModBusNet)
            Net: 'in1[0]' (ModBusNetBit)
                Equiv:	out[0]
            Net: 'in1[2:0]' (ModBusNet)
            Net: 'out[0]' (ModBusNetBit)
                Equiv:	in1[0]
            Net: 'out[0:2]' (ModBusNet)
    Contents of module child
            Term: 'grnd' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		'grnd'
        	Position:	3
            Term: 'powr' (ModScalarTerm)
        	TermType:	inputOutput
        	NumBits:	1
        	Net:		'powr'
        	Position:	2
            Term: 'y' (ModScalarTerm)
        	TermType:	output
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        	Net:		'y'
        	Position:	1
            Term: 'a' (ModScalarTerm)
        	TermType:	input
        	NumBits:	1
        	Net:		'a'
        	Position:	0
            Net: 'CK' (ModScalarNet)
            Net: 'grnd' (ModScalarNet)
            Net: 'powr' (ModScalarNet)
            Net: 'y' (ModScalarNet)
            Net: 'a' (ModScalarNet)
    Contents of TOP module top
            Term: 'out[31:0]' (ModBusTerm)
        	TermType:	output
        	NumBits:	32
        	Net:		'out[31:0]'
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            Term: 'in[31:0]' (ModBusTerm)
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        	Net:		'in[31:0]'
        	Position:	0
            Net: 'z' (ModScalarNet)
            Net: 'y' (ModScalarNet)
            Net: 'x' (ModScalarNet)
            Net: 'w' (ModScalarNet)
            Net: 'tie0' (ModScalarNet)
            SigType:	tieLo
            Global:	true
            Net: '32*tie0' (ModBundleNet)
            Net: 'done' (ModScalarNet)
            Net: 'prod[12:0]' (ModBusNet)
            Net: 'mcnd[12:0]' (ModBusNet)
            Net: 'ck' (ModScalarNet)
            Net: 'ir[15:0]' (ModBusNet)
            Net: 'acc[12:0]' (ModBusNet)
            Net: 'pc[12:0]' (ModBusNet)
            Net: 'n[1]' (ModBusNetBit)
            Net: 'go' (ModScalarNet)
            Net: 'int[0:31]' (ModBusNet)
            Net: 'out[31:0]' (ModBusNet)
            Net: 'in[31:0]' (ModBusNet)
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        	Is Bound:		yes
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        ModInst:
        	Is Bound:		yes
        	InstName:		I1
        	Master Cell Name:	child
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        	Net:	z
        	Inst:	I1
	Posit:	3 (bound to 'grnd')
        ModInstTerm:
        	Net:	y
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	Posit:	2 (bound to 'powr')
        ModInstTerm:
        	Net:	x
        	Inst:	I1
	Posit:	1 (bound to 'y')
        ModInstTerm:
        	Net:	w
        	Inst:	I1
	Posit:	0 (bound to 'a')



Reader succeeded