designhierout.ref

openaccess与verilog互相转化时所用的源代码

// Verilog file for cell "top" view "netlist" 
// Language Version: 2001 

module leaf (
    A,
    Q);

    input A;
    output Q;

endmodule // leaf


module mid (
    B,
    R);

    input B;
    input R;


    leaf I0 (
            .A(B),
            .Q(R));
endmodule // mid


module top ();

    wire C;
    wire S;

    mid I1 (
            .B(C),
            .R(S));
    leaf I2 (
            .A(C),
            .Q(S));
endmodule // top