globaltop.v

openaccess与verilog互相转化时所用的源代码

module globals;
    wire	    globalNet;
    wire    [1:0]   globalBus;
endmodule



module global1(input [31:0]  l1_in,
	      output        l1_out);
 	reg l1_reg;
endmodule

module global2A(inout [1:0] l2Aio);
	global1 I1(1, globals.globalNet);
endmodule


module global2B(inout [1:0] l2Bio);
	global1 I1('h80000000, globals.globalBus[0]);
endmodule


module top;
        supply1 myTie1;
        supply0 myTie0;
        
	global2A I1A({myTie1, myTie0});
	global2B I2B(2'b01);
	global2B J2B(.l2Bio(globals.globalBus[1:0]));
endmodule